Browse Prior Art Database

Intelligent Display System

IP.com Disclosure Number: IPCOM000110837D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 94K

Publishing Venue

IBM

Related People

Ilas, WJ: AUTHOR [+3]

Abstract

In many microprocessor systems, no facility exists to relay system information to the user. Users must often rely on computer-based debug monitor programs to obtain the status of the microprocessor system being evaluated. It is not always convenient and/or possible to connect a computer-based debugger to such systems. It is for this reason that it is desirable for a microprocessor system to contain a facility for displaying system prompts and status messages.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Intelligent Display System

      In many microprocessor systems, no facility exists to relay
system information to the user.  Users must often rely on
computer-based debug monitor programs to obtain the status of the
microprocessor system being evaluated.  It is not always convenient
and/or possible to connect a computer-based debugger to such systems.
It is for this reason that it is desirable for a microprocessor
system to contain a facility for displaying system prompts and status
messages.

      The Intelligent Display System (IDS) is designed to provide a
means for system information to be relayed to the user of a
microprocessor system.  This information is relayed to the user via
an eight-character alphanumeric display.

      The IDS hardware provides all the proper interfacing and
control signals to the display, removing this burden from the host
processor.  The user is given a full instruction set, allowing easy
access to all of the display's built-in features and to some
additional features provided by the IDS hardware.  These control
values can be passed to the IDS just like regular character values
and require no special processing by the host processor.  The host
processor needs only to send the character/control value bytes to the
IDS; all additional processing is handled by the IDS hardware.

      The IDS is composed of five main components.  An overall block
diagram for these components and their interconnections is shown in
Figure 1.

      Once the IDS is interfaced to its host processor system, it is
ready to receive information to either be displayed on the
alphanumeric display, or to change the operational parameters of the
display.  Incoming bytes are processed by the FIFO control logic and
then placed into the nine-bit wide FIFO memory.  Once an incoming
byte has been placed into the FIFO, the display control logic removes
the byte from the FIFO and processes it as either a display control
character or a displayable character value.  This FIFO allows the
host processor to send a block of data to the IDS and then be free to
do other processor tasks while the IDS sequences the data out of the
FIFO and processes it appropriately.

      The time delay module is used to generate user-programmable
delays between display updates.  This allow...