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Browse Prior Art Database

Power Reduction Technique for Programmable Delay Chains

IP.com Disclosure Number: IPCOM000110842D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 171K

Publishing Venue

IBM

Related People

Correale Jr, A: AUTHOR [+2]

Abstract

Precision circuitry implemented for use in programmable delay lines is mostly concerned with the overall delay accuracy and compensation for process and environmental variations with little regard for power dissipation. The circuits illustrated in this disclosure address power reduction without affecting the critical delay attributes of the circuit.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 36% of the total text.

Power Reduction Technique for Programmable Delay Chains

      Precision circuitry implemented for use in programmable delay
lines is mostly concerned with the overall delay accuracy and
compensation for process and environmental variations with little
regard for power dissipation.  The circuits illustrated in this
disclosure address power reduction without affecting the critical
delay attributes of the circuit.

      A typical programmable delay chain is illustrated in Fig. 1.
The chain is comprised of inverting delay elements, re-drive
inverting buffers, and a selector to select the desired tap.  The
delay element is comprised of four series transistors; the top two
are PFETs, and the bottom two are NFETs.  The uppermost device, Q1,
has its source connected to the power supply, drain connected to the
source of the second series PFET Q2, and gate connected to the output
of a voltage bias regulator Vp.  The drain of device Q2 is connected
to both the output of the delay element and the drain of the
uppermost NFET Q3.  The gates of both Q2 and Q3 are commoned and
establish the input to the delay element.  The source of device Q3 is
connected to the drain of the lowermost NFET Q4.  The source of
device Q4 is connected to ground.  The gate of Q4 is connected to the
output of another voltage bias regulator, Vn.  The output of this
delay element drives another delay element, which in turn drives
another delay element for the specified number of delay stages.  To
minimize delay variation at the output of the delay element due to
wiring and placement relative to the input of the selector, an
isolation inverter is typically used.  This inverter is comprised of
a PFET Q5, whose source is connected to the VDD, drain connected to
both the drain of NFET Q6, and one input to the selector gate
connected to both the gate of NFET Q6 and the output of the bias
compensated delay element, and finally the source of NFET Q6 is
connected to ground.  The output of this inverter drives one input of
the selector.  The selector has an associated decoder to select one
of the 'n' potential tap points from the 'n' stage delay chain.

      The selector, in many realizations, utilizes input buffer
isolation to minimize input capacitance and eliminate unwanted
effects if pass transistors are employed.  Furthermore, for large
delay chains, e.g., 16 states, type selectors are generally comprised
of multiple tiers of smaller input width selectors rather than a
single full input width realization.  Also, simplified decode schemes
may be employed wherein an individual selector may actually be
realized as multiple stages of select.

      The input to the delay chain is any signal requiring delay
compensation.  Many times, these signals are clocks that require
re-synchronization with others and, as such, can be running at high
frequency.

      The operation of the above delay circuit is described as
follows:  A static decode signal is appli...