Browse Prior Art Database

High-Speed Data Streaming for Existing Personal Computers

IP.com Disclosure Number: IPCOM000110854D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 114K

Publishing Venue

IBM

Related People

Capps Jr, LB: AUTHOR [+6]

Abstract

Described is a hardware implementation to add-in high-speed data streaming capability to Personal Computers (PCs) equipped with a Micro Channel* (MC). The implementation involves the use of interleaving buffers for 16- and 32-bit master access configurations and a small amount of control logic. A total redesign of the system is therefore not required to add-in data streaming capability to existing PCs.

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This is the abbreviated version, containing approximately 52% of the total text.

High-Speed Data Streaming for Existing Personal Computers

      Described is a hardware implementation to add-in high-speed
data streaming capability to Personal Computers (PCs) equipped with a
Micro Channel* (MC).  The implementation involves the use of
interleaving buffers for 16- and 32-bit master access configurations
and a small amount of control logic.  A total redesign of the system
is therefore not required to add-in data streaming capability to
existing PCs.

      Typically, the use of an expansion bus in a PC allows different
features to be added so that the computer can communicate with
peripherals, such as hard disks, printers, or computer networks.  In
many applications, the architecture of the PC expansion bus
determines, in large part, the overall performance of the PC.
Because of this, expansion bus architectures, such as the MC, are
enhanced to improve reliability and to increase data throughput.

      One of the most important enhancements to the MC is the
addition of streaming data which allows the PC to double the rate
that it communicates with expansion features on the MC.  The
implementation of the streaming data support is generally complex in
that it requires the streaming logic to become an integral part of
not only the MC interface logic, but also the system memory
controller.  Generally, the memory controller and the MC logic are
implemented in gate arrays which require the design of the streaming
logic to be implemented up front.

      The concept described herein provides a method whereby existing
PC designs can take advantage of the streaming data capability
without a total redesign of the PC by using existing gate arrays.  In
addition, new designs can use this method to implement streaming data
quickly, thereby providing a substantial system performance
improvement with minimum cost.

      The circuitry used to attain the data streaming capability in
existing PCs provides a means for a PC that has a 64-bit interleaved
Central Processing Unit (CPU) to memory interface.  It provides a
means to support streaming data type transfers on its MC system bus
to bus-master adapters that support data streaming.  Typically, when
a bus-master on the MC accesses the system memory, only the data that
the bus-master requests is read from memor...