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Browse Prior Art Database

DMA Controller Channel Interlocking

IP.com Disclosure Number: IPCOM000110870D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 6 page(s) / 178K

Publishing Venue

IBM

Related People

Palmer, MJ: AUTHOR

Abstract

In high performance disk file controllers the data passing between host system and disk drive passes through a data buffer, which is controlled by a DMA controller function. In many cases, the data will be written into the buffer by one DMA channel and read out of the buffer by another channel simultaneously. It is desirable to have the reading channel as close behind the writing channel as possible, while not attempting to fetch data from the buffer before it is stored into it. A solution is to have a hardware interlocking scheme that stops and starts the reading channel automatically based upon how much data is ready in the buffer for it to transfer. The scheme must work with the following:

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 37% of the total text.

DMA Controller Channel Interlocking

      In high performance disk file controllers the data passing
between host system and disk drive passes through a data buffer,
which is controlled by a DMA controller function.  In many cases, the
data will be written into the buffer by one DMA channel and read out
of the buffer by another channel simultaneously.  It is desirable to
have the reading channel as close behind the writing channel as
possible, while not attempting to fetch data from the buffer before
it is stored into it.  A solution is to have a hardware interlocking
scheme that stops and starts the reading channel automatically based
upon how much data is ready in the buffer for it to transfer.  The
scheme must work with the following:

o   Large numbers (e.g., 16) of channels, with arbitrary allocation
    of groups which are interlocked.

o   'Striping', where several channels are storing data interleaved
    into the data buffer, and one is fetching it out.

o   Address pointers which wrap, i.e., when they reach the end of a
    section of buffer, they return to the beginning.  The size of a
    buffer section is a power of 2, and is adjustable.

      This disclosed design is part of a DMA controller, coordinating
data transfer between DMA slaves and a shared data buffer.  The
diagram below shows an example with two DMA slaves.

When set, this bit prevents the channel from starting a DMA burst.

      One set of DMA channel registers is provided for each DMA
channel.  Each DMA channel register consists of 5 consecutive words;
the important ones for this scheme are explained below.  INTLCK    A
5-bit field, used to chain DMA channels which are to be
          hardware interlocked.  It contains the channel number of an
          associated DMA channel.  If a channel is not to be
interlocked
          with any other channel, then this field should be set to
point
          to itself.

CTRL      includes the Direction bit (1=Fetch, 0=Store).

INTLV     A 2-bit field controlling address incrementing and
wrapping.

                    00 = normal
                    10 = 2-way interleave
                    11 = 4-way interleave

ADDRESS   A 22-bit address pointer is provided.  The address pointers
          will automatically wrap when they reach the end of a buffer
          section.  (Size of a buffer section is specified in a DMA
          Control register; it is a power of 2.)  When operating with
          interleaved DASDS the pointers will be automatically
          incremented by 1 sector length (2-way interleave) or 3

sector
          lengths (4-way interleave) when a sector boundary is
          encountered.

ENABLE    This field includes the wait bit which is automatically set
          and reset during the address in...