Browse Prior Art Database

Unified Fixed and Floating Point Stores

IP.com Disclosure Number: IPCOM000110873D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Beacom, TJ: AUTHOR [+2]

Abstract

Disclosed is a method of using the available physical registers in a Floating Point Unit to hold the fixed point store data of a system with a single store queue. The same facilities used for register renaming can be used to hold the fixed point data.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 58% of the total text.

Unified Fixed and Floating Point Stores

      Disclosed is a method of using the available physical registers
in a Floating Point Unit to hold the fixed point store data of a
system with a single store queue.  The same facilities used for
register renaming can be used to hold the fixed point data.

      By making a Fixed Point Store appear simultaneously like a
Floating Point Load and a Floating Point Store, much of the existing
register renaming logic can be used.  The affects are outlined below.
Since a Floating Point Load initiates a "remapping" (an assignment of
a Floating Point Register (FPR) to a new physical register), an
available physical register will be delivered (the Load Available
Queue provides an address of an unused register).  The Fixed Point
Store data will then be written to that physical register just like
Floating Point Load data.  Since the instruction also looks like a
Floating Point Store, information related to the instruction will be
entered into the Floating Point Store Queue.  The addresses of the
register to be stored (which is written to the Store Queue) must be
the same address that the data was written to and so will also be
obtained from the Load Available Queue (see New Path #1 in the
Figure).

      The addresses of the physical registers move through the rename
logic on several connected loops.  All physical addresses must exist
in one and only one location within these loops.  When an address
leaves an Available Queue...