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Browse Prior Art Database

Micro Channel Programmable Option to Improve Channel Bandwidth

IP.com Disclosure Number: IPCOM000110890D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 113K

Publishing Venue

IBM

Related People

Farrell, JK: AUTHOR [+9]

Abstract

Described is an architectural implementation to provide a programmable option for personal computers equipped with a Micro Channel* (MC). The implementation is designed to improve channel bandwidth by appending input/output (I/O) transfers.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 50% of the total text.

Micro Channel Programmable Option to Improve Channel Bandwidth

      Described is an architectural implementation to provide a
programmable option for personal computers equipped with a Micro
Channel* (MC).  The implementation is designed to improve channel
bandwidth by appending input/output (I/O) transfers.

      In prior art, no simple solutions existed for improving the
bandwidth of peer operations across a MC.  Regardless of whether a
peer-to-peer operation is a command or a data transfer, peer
operations generally consisted of a transfer, by a bus master, of
some data followed by an I/O operation used for signaling the slave
device that the transfer has been completed.  In peer-to-peer
communications between subsystems across the MC, the channel
bandwidth could be lost between data transfer and signaling
operations.  This loss occurred because bus master designs were
simple Direct Memory Access (DMA) channels that required
reprogramming after each data transfer in order to perform a
signaling operation.

      The concept described herein creates a programmable option for
a MC bus master to append a single I/O write after a data transfer to
signal the MC slave.  The I/O write is used to support the method of
signaling defined in the Subsystem Control Block (SCB) architecture.
However, the function can be used to enable a write operation of any
data to any I/O location in the MC address space.

      Typically, bus masters tend to fall into two categories -
simple DMA channel designs and high bandwidth designs.  In simple DMA
channel designs, although cost effective, they do not address
bandwidth considerations.  In high bandwidth designs, the designs are
complex and generally handle bandwidth issues by combining transfers
between a master and several slaves within a single ownership of the
MC, and/or by using private protocols across the MC to establish high
speed data transfers.  The use of the MC in these two categories
generally involves an intelligent DMA controller that can poll
several slaves and thereby increase the bandwidth by doing several
peer-to-peer operations in a single bus ownership.

      The concept is designed to provide a cost effective performance
alternative between the two above categories.  Recognizing that most
peer-to-peer operations involve a data transfer followed by a
signaling operation, the concept improves on the simple DMA channel
design by allowing the channel to perform both operations without
reprogramming the DMA channel.  This appended I/O operation is
controlled as a programmable option in the DMA channel's control
register.

The appended I/O feature has the following advantages:

o   For bus master writes to the MC, the signaling I/O transfer can
    be appended directly to the data transfer.

o   For both bus master reads and writes to the MC, the signaling I/O
    transfer occurs with no additional programming of the DMA
    channel, i.e., the address a...