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Layout for Improved Testability of Six-Device Static Random-Access Memory Cells

IP.com Disclosure Number: IPCOM000110896D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Bertolet, AR: AUTHOR [+5]

Abstract

By making straps for cross-coupling the two inverters of a standard Static Random-Access Memory (SRAM) cell of silicide conductor instead of first level metal and connected in a manner such that a gate open as well as a pull-up open is caused when connection failure occurs, a failure mode which is hard to detect is reduced. An open in connections made in the new wiring design results in inability to write into the cell instead of having possible loss of data over an indeterminate time period.

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Layout for Improved Testability of Six-Device Static Random-Access
Memory Cells

      By making straps for cross-coupling the two inverters of a
standard Static Random-Access Memory (SRAM) cell of silicide
conductor instead of first level metal and connected in a manner such
that a gate open as well as a pull-up open is caused when connection
failure occurs, a failure mode which is hard to detect is reduced.
An open in connections made in the new wiring design results in
inability to write into the cell instead of having possible loss of
data over an indeterminate time period.

      Referring to Fig. 1, a standard six-device SRAM cell is shown.
It is comprised of N-type pass gate transistors T1 and T2 having
their gates connected to word line WL and output to True and
Complement bit lines BLT and BLC respectively.  P-type pull-up
transistor T3 and N-type transistor T5 make up a first inverter which
is cross-coupled to a second inverter made up of pull-up transistor
T4 connected to N-type transistor T6.  Lines L1 and L2 are
conventionally formed by first level metal lines.  An open in a
connection within L1 or L2 does not stop ability to write, store, and
read data but does cause loss of that data over some indeterminate
period of time.

      Referring to Fig. 2, the same latch configuration is wired to
have dashed lines L1 and L2 made of silicide and configured to also
cause an open in cross-coupling to gates of the inverters when an
open occurs in drain co...