Browse Prior Art Database

Power Reduction Technique for Chips using Common I/O

IP.com Disclosure Number: IPCOM000110907D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 6 page(s) / 177K

Publishing Venue

IBM

Related People

Correale Jr, A: AUTHOR

Abstract

Traditionally, chips using common I/O allow the receive logic to "listen" while the driver is active. This "listening" results in the circuitry comprising the receiver and the associated downstream logic to switch unnecessarily, thereby creating unnecessary noise and power dissipation. A typical Common I/O and its associated logic clouds are illustrated in Fig. 1. The common I/O is comprised of a tri-state driver and a receiver. The tri-state control, when deactivated, directs the driver to output its data to the system. The tri-state control, when activated, directs the driver into a non-controlling high impedance output state, thereby relinquishing control of the bus. When this driver is tri-stated, another device on the common bus has control and its data is presented to the system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 50% of the total text.

Power Reduction Technique for Chips using Common I/O

      Traditionally, chips using common I/O allow the receive logic
to "listen" while the driver is active.  This "listening" results in
the circuitry comprising the receiver and the associated downstream
logic to switch unnecessarily, thereby creating unnecessary noise and
power dissipation.  A typical Common I/O and its associated logic
clouds are illustrated in Fig. 1.  The common I/O is comprised of a
tri-state driver and a receiver.  The tri-state control, when
deactivated, directs the driver to output its data to the system.
The tri-state control, when activated, directs the driver into a
non-controlling high impedance output state, thereby relinquishing
control of the bus.  When this driver is tri-stated, another device
on the common bus has control and its data is presented to the
system.  The receiver traditionally has only a data input without any
disabling control.  During both operations, the receiver is
"listening" and responding to the stimulus.  Furthermore, the
downstream logic up to the capture latch's output is also responding
to the stimulus.  This may be appropriate during a "read" operation
where listening is intentional.  Clearly, when the driver has control
(non-tri-stated), the accompanying receiver and its downstream logic
should not be responding to its output.  This can be effectively
controlled rather simply with the benefits of reduced noise and power
dissipation.

      Fig. 2 illustrates a modified common I/O structure wherein the
receiver has been modified and some additional control logic
introduced.  In this case, the receiver has been enhanced with the
addition of a control line to effectively tri-state its output.
Tri-stating the output of the receiver alone will result in undefined
internal logic states over time as these nodes are now "dynamic", and
as such, increased power dissipation can occur as voltage levels
drift.  Therefore, two options are available: 1) tri-state the
receiver and force its output to a given state, e.g., a logical "0",
or 2) integrate a very small, low power data holding latch within the
receiver.  The first option can be very effective if the frequency of
the common I/O in read mode is low, as the forcing of the output
occurs infrequently.  Since the output is always going to be forced
independent of the prior state, there is a probability that it
created a switch.  Hence, the effectiveness is a function of read
frequency.  The choice of the second option results in a receiver
that will "hold" its prior state when the control input is activated.
This holding of the previous state will ensure no switching activity
of the elements from the receiver to the downstream capture logic and
will ensure defined logic states through the path.  This realization
is effective for optimal power reduction regardless of the read
frequency.

      Fig. 3 illustrates a block diagram of the enhanced receiver
utilizing...