Browse Prior Art Database

Data Bus Synchronization Mechanism

IP.com Disclosure Number: IPCOM000110910D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Drehmel, RA: AUTHOR [+2]

Abstract

A method for synchronizing data received from one bus to another that has a much higher transfer rate is disclosed. The invention provides a mechanism to synchronize and stream data from a DRAM bus to a processor bus that runs several times faster.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 88% of the total text.

Data Bus Synchronization Mechanism

      A method for synchronizing data received from one bus to
another that has a much higher transfer rate is disclosed.  The
invention provides a mechanism to synchronize and stream data from a
DRAM bus to a processor bus that runs several times faster.

      The invention adds a synchronization (GAP) bit to the data
transfer.  The supplier (the memory card) starts the data transfer as
soon as it has data to transfer to the requester (the processor).
During the time that it does not have valid data (i.e., while
fetching more data from the DRAMs), it activates the GAP bit.  The
bit indicates to the receiver that the data is not valid and should
be ignored.  The GAP bit is treated like another data bit and is
included in the ECC word.

A data transfer may occur as follows:

o   The data supplier indicates that it has data to transfer.

o   The data transfer is started.

o   The GAP bit indicates to use/don't use the data.

o   All of the data is transferred.

      The Figure shows a pattern of data,data,gap,gap,etc.  This
pattern is dependent on when the data bus is won and where data is in
the memory card data pipe.  For example, if the data bus is busy
(from other devices) and the memory can't win for several cycles, all
of the data may be in the card and there will not be any gaps.

The invention meets the following requirements:

o   The sender must arbitrate and win the bus before sending the
    data.

o  ...