Browse Prior Art Database

Shared Decoder for Array Macros

IP.com Disclosure Number: IPCOM000110941D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Aipperspach, AG: AUTHOR [+2]

Abstract

Disclosed is a fast static decoder (shared decoder) which selects one of all output lines when a clock and an enable signal are applied.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Shared Decoder for Array Macros

      Disclosed is a fast static decoder (shared decoder) which
selects one of all output lines when a clock and an enable signal are
applied.

      The Figure shows schematically the shared decoder scheme.  A
simplified case of 4 address inputs and 2-bit decoders is shown.
True and complement of each incoming address bit feed the 2-bit
decoders.  By arranging the decoders in the order shown, each decoder
is able to service 2 DOT-NOR circuits to produce the 16 decoded
outputs.  A 4-bit decode function can be realized in a fashion that
only requires a 2-bit decoder to be layed out at the pitch of the
storage array cell, thereby reducing the true/complement generator
loading by one half and optimumizing the decoder layout for very
short wire lengths.