Browse Prior Art Database

Master/Slave Method for Path-Width Expansion in Asynchronous Networks

IP.com Disclosure Number: IPCOM000110949D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Olnowich, HT: AUTHOR

Abstract

Disclosed is a method for increasing the bandwidth of asynchronous multi-stage networks using the lower risk and more conventional approach of expanding the data path width, as opposed to increasing the frequency of transmission. The method uses two smaller and less expensive switch chips in parallel, as opposed to building larger and more expensive switch chips that would internally contain double the path width. The disclosed method, besides being a more cost effective solution, provides unlimited bandwidth expansion by paralleling 3, 4 or more switch chips to vastly improve the network bandwidth.

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Master/Slave Method for Path-Width Expansion in Asynchronous Networks

      Disclosed is a method for increasing the bandwidth of
asynchronous multi-stage networks using the lower risk and more
conventional approach of expanding the data path width, as opposed to
increasing the frequency of transmission.  The method uses two
smaller and less expensive switch chips in parallel, as opposed to
building larger and more expensive switch chips that would internally
contain double the path width.  The disclosed method, besides being a
more cost effective solution, provides unlimited bandwidth expansion
by paralleling 3, 4 or more switch chips to vastly improve the
network bandwidth.

      For asynchronous networks, data-width expansion is not
straightforward, like it is with synchronous networks.  The problem
is how to keep the parallel data paths aligned and error-free as they
traverse parallel switch chips which have no common synchronous
clocks.

      The Figure illustrates the general solution by showing three
8x8 switch chips (10A, 10B and 10C) in parallel to triple the basic
network bandwidth.  Each switch chip provides a unit of data width,
which can be variable from 1 to n bits.  The three asynchronous
switch chips are kept aligned using a master/slave synchronization
technique.  Master switch chips are differentiated from slave switch
chips by putting a new chip I/O pin called "M/S" to either a ground
or up level externally.  A ground level defines to...