Browse Prior Art Database

Two-Stage Microcode Support using Flash EEPROMS

IP.com Disclosure Number: IPCOM000110953D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 153K

Publishing Venue

IBM

Related People

Capps Jr, LB: AUTHOR [+5]

Abstract

Described is an architectural implementation to provide a two-stage Power-On System Test (POST) and Basic Input/Output System (BIOS) microcode support using FLASH Electronically Erasable Programmable Read-Only Memory (EEPROM) devices for use in Personal Computer (PC) systems.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 33% of the total text.

Two-Stage Microcode Support using Flash EEPROMS

      Described is an architectural implementation to provide a
two-stage Power-On System Test (POST) and Basic Input/Output System
(BIOS) microcode support using FLASH Electronically Erasable
Programmable Read-Only Memory (EEPROM) devices for use in Personal
Computer (PC) systems.

      The two-stage microcode support is an improvement over a
previous implementation in that it provides for organizing and
updating 256K of PC system boot microcode in two 128K FLASH EEPROMs.
The intent is to eliminate any possibility of having an inoperable
system resulting from a power failure.

      Typically, PC systems use POST software or microcode to test
the system when it is first powered ON.  The microcode is stored in
hardware type of devices, such as ROMs, since the microcode is needed
immediately after the system is powered ON and before any peripheral
devices are actuated.  This same ROM is used to hold the BIOS
microcode that is used by the operating system to interface to the
system hardware.  However, once the system is in use, additional
feature adapters may be added which can require changes to the POST
or BIOS microcode requiring ROM upgrading.  To overcome extensive
upgrading, an Initial Program Load (IML) feature was implemented in
prior art that allowed two 128K POST/BIOS microcode images to be used
instead of just one 128K ROM microcode image.  The first stage 128K
image was still located in ROM while the second stage 128K image was
kept on a peripheral storage device, such as a hardfile.  This
enabled the second stage 128K image, containing the POST/BIOS
microcode to be updated electronically without a ROM change.
However, with the IML, special disk controllers were required that
supported the storage of the second stage 128K image.  In addition,
if the hardfile required replacement, the second stage 128K image was
no longer available, and since the first stage 128K image microcode
was still in ROM, it could not electronically be upgradable.

      Since the IML was introduced, FLASH EEPROM technology can be
used during power-up, similar to ROMs, but reprogrammed
electronically like IML.  Since FLASH EEPROMs are completely
erasable, a typical approach to using FLASH EEPROM technology would
be to store the total Stage 1 and Stage 2 microcode images from ROM
and the IML (256K) in a single FLASH EEPROM part.  However, because
the FLASH EEPROM must be completely erased before any new
programming, a power failure during the update process could render
the system inoperable, resulting in a system with no boot microcode.
Prior art utilized redundant storage units to remove the possibility
of having an inoperable system.  In this prior-art approach, both
128K FLASH EEPROM parts contained the same image so the if one image
was destroyed, the other would always be a back-up.  However, with
this prior-art approach, only 128K of microcode was stored.

      The concept...