Browse Prior Art Database

Slave Synchronization Interface for Parallel Network Paths

IP.com Disclosure Number: IPCOM000110983D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Olnowich, HT: AUTHOR

Abstract

Disclosed is a master/slave interface for synchronizing multi-stage networks comprised of asynchronous switch chips for use in parallel to improve network bandwidth.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Slave Synchronization Interface for Parallel Network Paths

      Disclosed is a master/slave interface for synchronizing
multi-stage networks comprised of asynchronous switch chips for use
in parallel to improve network bandwidth.

      For asynchronous networks, when switch chips are to be used in
parallel to expand the network data width, the paralleled switch
chips can be kept in synchronization using the disclosed Master/Slave
Synchronization Interface.  One of the paralleled switch chips is
designated as master, and the remainder as slaves.  The master chip
reflects any decisions it makes over the disclosed switch-to-switch
synchronization interface, called the Slave Selection Control
interface, as shown in the Figure.

      The Slave Selection Control Interface can be implemented in
various ways.  Option 1, the lowest latency approach, would require a
total of 32 parallel signal lines, as shown in the Figure.  Four
signal lines are associated with each master switch chip output port,
assuming there are 8 output ports per switch chip.  One line in each
set of 4 would indicate whether the associated output port was
connected or not, and the other 3 lines would indicate to which of
the 8 input ports it was connected.  These sets of 4 lines would each
directly control the connection of an associated output port in the
slave chips.  A variation of this approach would use the sets of 4
lines as follows:  3 lines would indicate to which of the 8 input
ports the associated output port was connected, and the 4th...