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Multi-Position Shift Registers for Programmable Width Pipes

IP.com Disclosure Number: IPCOM000110985D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 132K

Publishing Venue

IBM

Related People

Gyllenhammer, CR: AUTHOR [+2]

Abstract

There are many occasions where the width of an output bus is made programmable to increase the flexibility of the design. Usually, this type of programmability uses a set of Multiplexors (selectors) placed after a register stage in the pipe to "steer" in the correct bits during the correct cycle.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multi-Position Shift Registers for Programmable Width Pipes

      There are many occasions where the width of an output bus is
made programmable to increase the flexibility of the design.
Usually, this type of programmability uses a set of Multiplexors
(selectors) placed after a register stage in the pipe to "steer" in
the correct bits during the correct cycle.

      A better alternative is to use a multi-position shift register
to do the data steering.  A multiposition shift register uses a set
of multiplexors (MUXes) at the inputs to feed the outputs back into
the register.  This allows the data to be "shifted" within the
register to the proper positions.  The control of the shift register
is very simple, and the logic between the register and the output has
been removed to eliminate the skew.

      Standard programmable width pipes are designed using the
structure in Fig. 1.  The MUXes after the registers (REGS) are used
to steer different register bits to the output during different
cycles, depending on the desired width of the output bus.  This skew
can become very significant for complex steering functions.
Secondly, as the type of data steering becomes more complex, the
logic needed to control the MUXes becomes very complex to design.

      A multi-position shift register has a structure shown in Fig.
2.  This structure places the MUXes before the register state, and
the output bus is connected directly to the register outputs.

      The MUXes on the input are used to either load a new value into
the register or feed the outputs of the register back in the register
so that the next transfer to the output bus can be "waiting" at the
correct input.  Therefore, when the register is clocked again, the
correct bits will be latched into the proper locations.

      This structure has two major advantages over the standard
solution.  First, there is no logic between the output bus and the
register.  Second, the control logic for the steering function is
trivial.

      The example in Table 1 consists of a complex function.  (The
function described is similar to the function of the cursor update
logic for video adapters.)  The function is the following:

o   A 64-bit data stream must be periodically sent to an output bus.

o   An Address compare is done to determine when 64 bits of
    information are to be placed onto the bus.  The address compare
    is done on the bit boundary.

o   If there is no address match, the output bus is forced to zeros.

o   The 64-bit data stream can start on any bit of the output data
    bus.  (That is, if the data bus was 4 bits wide, the first bit of
    the data stream could be placed on bit 3,2,1 or 0 of the output
   ...