Simultaneous Read Access of Multiple Independent Read-Only Memory Addresses
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Disclosed is a circuit which allows multiple independent, simultaneous read accesses to a latch-based Read-Only Memory (ROM).
Simultaneous Read Access of Multiple Independent
a circuit which allows multiple independent,
simultaneous read accesses to a latch-based Read-Only Memory (ROM).
latch-based ROM, each latch holds a single bit of data.
Therefore, the total number of latches required to implement a ROM
equals the total number of bits in the memory. Applications exist,
such as computing Fast Fourier Transforms or Discrete Cosine
Transforms, where the sum of product calculations are performed using
distributed arithmetic techniques. Distributed arithmetic sums
predetermined coefficients stored in ROMs to arrive at a sum of
products, thereby eliminating the need for multiplication hardware.
To speed the summation, designs perform the summation operation 2
bits at a time, using two exact copies of the coefficients in two
independent ROMs. This approach doubles the number of bits of ROM
incorporated into the hardware design and therefore doubles the
number of latches. The circuit shown in the Figure permits a single
copy of the coefficients to exist in a single read-only memory yet
allows simultaneous, independent access to two memory addresses.
shows 4 bits of memory in bit position n of 4
individual memory words. Decoder circuits generate the address
select signals from two independent input addresses. In this
configuration, registers receive the data bits. This is an example
of a two-word simul...