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Zero Cache Line Within Array

IP.com Disclosure Number: IPCOM000111009D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Braceras, GM: AUTHOR [+2]

Abstract

At times it is necessary for the processor to zero a data line, a page, or even a large block of memory. One way to achieve this is to have the execution unit perform repeated word stores to the cache array. For a 64 word line and a word wide bus this would require 64 word transfers of 0's from the execution unit and would tie up the processor for 64 cycles. Another approach is to place 0's on a line's worth of inputs (64 words = 36 bits/word = 2304 bits) which feed into the array and performing a line write within the array.

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Zero Cache Line Within Array

      At times it is necessary for the processor to zero a data line,
a page, or even a large block of memory.  One way to achieve this is
to have the execution unit perform repeated word stores to the cache
array.  For a 64 word line and a word wide bus this would require 64
word transfers of 0's from the execution unit and would tie up the
processor for 64 cycles.  Another approach is to place 0's on a
line's worth of inputs (64 words = 36 bits/word = 2304 bits) which
feed into the array and performing a line write within the array.

      A function can be built into the array which will perform the
zeroing function more efficently than the above scenarios.  The array
has a single word input path to write a word into the array.  By
internally clamping this path to zeros within the array and exerting
the write marks for an entire line instead of a single word, the line
can be zeroed within a cycle.

      This function doesn't require 64 cycles to execute nor does it
need the 2304 additional inputs to the array and their associated
wiring.