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Browse Prior Art Database

Parity Checking of Synchronous Bus Control Signals

IP.com Disclosure Number: IPCOM000111041D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 121K

Publishing Venue

IBM

Related People

Keung, TW: AUTHOR [+3]

Abstract

Described is a hardware implementation to provide parity checking to data and/or addresses of synchronous bus control signals. The implementation is designed to maintain data integrity to increase the reliability and serviceability of computer systems.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Parity Checking of Synchronous Bus Control Signals

      Described is a hardware implementation to provide parity
checking to data and/or addresses of synchronous bus control signals.
The implementation is designed to maintain data integrity to increase
the reliability and serviceability of computer systems.

      The parity checking of synchronous bus control signals is
essentially an error detection device based on the following bus
features:

o   For every synchronous bus architecture, there is some combination
    of bus control signals defined to indicate the beginning of a bus
    cycle.  Also there is some combination of bus control signals
    defined to indicate the end of a bus cycle.  For example, an
    address strobe indicates the beginning and a ready indicates the
    end of a bus cycle.  A single signal is defined to indicate both

    the beginning and end point of a bus cycle.  A high to low
    transition for the beginning and a low to high transition for the
    end, or visa versa.

o   For the duration of a bus cycle, all the control signals are
    unidirectional, some from a master unit to a slave unit and some
    from a slave unit to a master unit.

o   At each sampling clock edge, the master unit and the slave unit
    will see the same value on a given control signal.

      Within each bus unit, logic is designed to capture the value of
the control signals at every sampling clock edge during a bus cycle.
The values of each control signal sampled during every sampling clock
edge are exclusive Or'd together to form a single control signal
parity bit.  During the next clock cycle, or at a later clock cycle
due to timing constraints, the control parity bit of the unit is
compared with the control signal parity bit of the slave unit.  A
difference in value will indicate a control signal error.

      Fig. 1 shows the configuration of the parity checking of
synchronous bus control signal circuit architecture.  The circuitry
consists of four distinct elements, as follows:

1.  Control signal sample parity generator 10 - The function of this
    generator is to generate a parity bit from the values of a
    control signal sampled during clock cycles of a bus cycle.  Fig.
    2a shows the operation of the control signal samples parity
    generator and Fig. 2b shows a timing chart of the parity
    generation.

2.  Control parity b...