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Power-on-Reset Circuit Sensitive to Power Supply Level and Clock

IP.com Disclosure Number: IPCOM000111048D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 87K

Publishing Venue

IBM

Related People

Bailey, JA: AUTHOR [+4]

Abstract

The function of a Power-On Reset (POR) circuit is to generate a -POR digital signal. An active -POR signal indicates that the circuits can be in a condition unsafe for logic operation. An inactive -POR indicates that certain conditions have been met, and it is safe for the circuits to operate. Safe operation of logic circuits requires a supply voltage level high enough for the logic to switch at clock rates and with adequate noise immunity. Additionally, if the logic requires a "clock reset" then a clock oscillator must also be functioning. For some logic this requires many clock transitions before all the logic can be reset; that is, a delay between the time that the supply voltage reaches a minimum specified threshold level and the time when the -POR goes inactive.

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This is the abbreviated version, containing approximately 52% of the total text.

Power-on-Reset Circuit Sensitive to Power Supply Level and Clock

      The function of a Power-On Reset (POR) circuit is to generate a
-POR digital signal.  An active -POR signal indicates that the
circuits can be in a condition unsafe for logic operation.  An
inactive -POR indicates that certain conditions have been met, and it
is safe for the circuits to operate.  Safe operation of logic
circuits requires a supply voltage level high enough for the logic to
switch at clock rates and with adequate noise immunity.
Additionally, if the logic requires a "clock reset" then a clock
oscillator must also be functioning.  For some logic this requires
many clock transitions before all the logic can be reset; that is, a
delay between the time that the supply voltage reaches a minimum
specified threshold level and the time when the -POR goes inactive.

      One method utilized in the past was to merely assume that the
clock was oscillating when the supply voltage reached a specified
level.  This avoids the need for additional circuits to detect a
clock.  A delay is usually generated with a very long digital counter
to provide adequate time for all the logic to be reset.  This method
is effective but requires additional logic to generate the long delay
and must assume that the clock is running.  A second method requires
a PLL circuit to detect the presence of a clock frequency.  A PLL
generates an error voltage signal proportional to the difference
between it free-running frequency and that of the incoming clock.  It
takes some time for the error voltage to reach steady state which
then guarantees the delay.  Using a PLL can be expensive because
external components are needed and that the delay realized will be
unreliable.

      A unique approach to these problems will save cost and space by
combining a Voltage Detector with a Transition Detector into one
integrated circuit.

      A functional block diagram of the integrated POR circuit is
shown in the Figure.  The function consists of a Voltage Level
detector, Clock Transiti...