Browse Prior Art Database

Multi-Card Synchronous Register Write

IP.com Disclosure Number: IPCOM000111050D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Haselhorst, KH: AUTHOR [+4]

Abstract

A method of synchronously writing multiple independent registers in parallel is disclosed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Multi-Card Synchronous Register Write

      A method of synchronously writing multiple independent
registers in parallel is disclosed.

      Use the IEEE 1149.1 standard (JTAG) interface to initiate a
write to a register.  A temporary Register Data Buffer is then used
to hold the register data until a synchronous pulse is received.  The
synchronous pulse then causes the data to be written into the
register.

1.  Using the JTAG Logic (1) initiate the register write to the
    required register.  The register write data is written into the
    Register Data Buffer (2) located on all chips.

2.  Repeat step one as required for each additional chips' registers.

3.  Enable the Sync Pulse (5) thereby gating the register write data,
    held in the Register Data Buffer (2), into the appropriate chip
    Register (4).  The Control (3) logic controls the transfer of the
    data from the Register Data Buffer (2) to the Register (4) when a
    Sync Pulse (5) is received.  Those chips which were not
    previously loaded with data will ignore the pulse.  All registers
    required are written in parallel at this point.

4.  The register write logic then resets for future register writes.