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Multichip Module with Two Memory Configurations

IP.com Disclosure Number: IPCOM000111052D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 94K

Publishing Venue

IBM

Related People

Countryman, GJ: AUTHOR [+3]

Abstract

A Common Multi-chip processor module is designed which can be used with a four or eight word memory subsystem, thus resulting in numerous savings. In a processor higher performance can be achieved with a wider memory bus. But there are physical costs associated with a wider bus such as extra chip I/O pins, extra planer wiring, added buffers to store the data, wider memory card connections or dual memory cards). Typically tradeoffs are made and a certain memory bus width is dictated.

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This is the abbreviated version, containing approximately 52% of the total text.

Multichip Module with Two Memory Configurations

      A Common Multi-chip processor module is designed which can be
used with a four or eight word memory subsystem, thus resulting in
numerous savings.  In a processor higher performance can be achieved
with a wider memory bus.  But there are physical costs associated
with a wider bus such as extra chip I/O pins, extra planer wiring,
added buffers to store the data, wider memory card connections or
dual memory cards).  Typically tradeoffs are made and a certain
memory bus width is dictated.

      Two systems are designed with different memory widths but share
the same multi-chip package.  One system is a high performance 8-word
system while the other is a lower performance 4-word system.

      The common multi-chip package created for both system
configurations results in numerous advantages.  For instance by using
the same chips in both configurations the internal busses between the
chips can be the same, therefore, only one multi-chip module needs to
be developed and kept in inventory.  Once the module is packaged with
the chips, the same chip-to-chip internal wiring test can be used for
both systems.  The external I/O test for the module used in a 4-word
system requires only a slight modification of the 8-word test to
accomadate the additional memory pins.  It is simple to run both
external I/O tests during module test and verify that the package is
good for either a 4 or 8-word system.  Once tested only one type of
package needs to be kept in inventory.  System manufacturing will
then have the flexibility to use the common package in either the 4
or 8-word systems depending on whichever is presently in demand.

      Thereby using the same chips interconnected identically on the
common chip package results in the greatest system savings when
considering the complete product development aspects (design,
testing, and manufacturing).

      The processor is designed in 8 chips which are mounted on the
common multi-chip package.  The functional signals which are brought
off of the package are an 8-word memory bus and a System I/O bus.  By
connecting only half of the memory bus pins and adding a mode input
pin, the 4-word system is easily constructed.  Additionally, the
Storage and Data Cache chips are designed internally to accept the
different memory widths and number of tranfer cycles.  The external
I/O bus is kept the same width to optimize I/O performance.

      Internally on the multichip module, the 8...