Browse Prior Art Database

Differential Emitter Dotted Multiplexor

IP.com Disclosure Number: IPCOM000111071D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Gillingham, RD: AUTHOR [+4]

Abstract

A design for a double buffered multiplexor is disclosed. The multiplexor (MUX) uses an emitter dotting configuration to obtain reduced circuit delay while maintaining isolation between inputs.

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Differential Emitter Dotted Multiplexor

      A design for a double buffered multiplexor is disclosed.  The
multiplexor (MUX) uses an emitter dotting configuration to obtain
reduced circuit delay while maintaining isolation between inputs.

      The multiplexor is shown in the Figure.  Each differential
input feeds an NPN differential pair.  The output of each of these is
emitter followed by NPN's Q6-Q8 and Q9-Q10.  The emitter followers
that correspond to different inputs but similar polarities are then
dotted together and biased by NPNs Q17 and Q16.

      When input B0-B1 is selected, differential input C0-C1 is
brought high (i.e., C0 is high and C1 is low).  This turns off
current to NPNs Q1,Q2 and Q4 so that signal from B2-B3 will not pass.
In addition to this NPN's Q11 and Q14 turn off while NPN's Q12 and
Q15 turn on, biasing the bases of Q9 and Q10 low, which turns them
off and further isolates inputs B2-B3 from the output 20-21.

      The reduced delay of the circuit arises because the input needs
only to pass through one differential stage and an emitter follower
as opposed to two differential stages, and the first differential
stage does not suffer from Miller capacitance loading effects of the
second differential pair.  This is particular useful if a 3:1 or 4:1
MUX is desired.