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Process-Variation-Tolerant Zero Skew Clock Routing

IP.com Disclosure Number: IPCOM000111077D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26

Publishing Venue

IBM

Related People

Lin, S: AUTHOR [+2]

Abstract

Disclosed is a new hierarchical two-stage multiple-merge zero skew clock routing algorithm. The routing results produced by the approach will have zero skew and minimal skew increase in the worst process-variation situation.

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Process-Variation-Tolerant Zero Skew Clock Routing

      Disclosed is a new hierarchical two-stage multiple-merge zero
skew clock routing algorithm.  The routing results produced by the
approach will have zero skew and minimal skew increase in the worst
process-variation situation.

      Skew is defined as the maximum delay difference from the clock
source to clock pins (destinations).  In synchronous circuit design,
skew sets the lower bound of clock cycle time; therefore, minimizing
clock skew is a very important problem in the design of high
performance VLSI systems.  The zero skew clock routing problem is to
construct a routing to connect all clock pins with the same delay
from the clock source to each clock pin.  Besides the clock pin
locations, the capacitive loading of each clock pin, and the per unit
wire length resistance (R) and capacitance (C) parameters are also
given as inputs for measuring delays.

      Ren-Song Tsay [*]  proposed a bottom-up binary-merge zero skew
routing algorithm.  His approach recursively merges two zero skew
subtrees to form a bigger zero skew subtree until the resulting zero
skew subtree contains all clock pins as its leaves.  The root of this
tree also determines the location of the clock source.  Fig. 1 shows
an example.  A, B, C are three clock pins to be routed.  At the first
step, A and B are merged.  Based on the Elemore RC delay model, we
can determine a tapping point D giving the same delay from D to A and
from D to B.  At the next step, the subtree containing the single pin
C and the subtree A-D-B are merged as shown in the figure.  The
tapping point E giving the same delay from E to C and from E to D
then A (or B) is the location of the clock soure.

However, the approach of [*]  suffers from the following two
drawbacks:

1.    It is vulnerable to process variation.  The routing result
    produced by [*]  is guided by estimated delays, which depend on
    the R C parameters and the capacitive loading of each clock pin.
    During the chip fabrication, any change of these parameters will
    incur severe skew increase.  Fig. 1 is an example.  If the actual
    R is larger than expected, since the wire length from E to C is
    longer than that from E to A, the delay increase at pin C will be
    larger, resulting in nonzero skew.  However, this kind of process
    variation commonly happens because those parameters are
    determined based solely on designers' prediction.

2.    It is lack of design flexiblity.  If designers want to modify
    the location of any clock pin, the entire clock routing needs
    redone to avoid skew.  The effect of modification is not local
    and will change the delays to most of the clock pins.  However,
    modifications commonly occur because designers cannot know the
    exact clock pin locations until the very last stage but, clock
    routing cannot be deferred to the last st...