Browse Prior Art Database

VRAM Controller Simplification Technique

IP.com Disclosure Number: IPCOM000111078D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 75K

Publishing Venue

IBM

Related People

Eiche, JS: AUTHOR [+2]

Abstract

Most Video RAM (VRAM) chips contain a Dynamic RAM (DRAM) to buffer Frame Data from digital sources and a Serial Data Register (SDR) to load parallel data from the DRAM in anticipation of clocking it serially to a display. See Fig. 1 for a generic diagram.

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VRAM Controller Simplification Technique

      Most Video RAM (VRAM) chips contain a Dynamic RAM (DRAM) to
buffer Frame Data from digital sources and a Serial Data Register
(SDR) to load parallel data from the DRAM in anticipation of clocking
it serially to a display.  See Fig. 1 for a generic diagram.

The primary modes of operation of a VRAM are:

1.  Loading the DRAM.

2.  Refreshing the DRAM.

3.  Loading the SDR.

4.  Clocking the SDR Serial Data out.

      The VRAM design only allows mode 4 to be performed
simultaneously with modes 1 and 2.  Modes 1, 2 and 3 must be
performed singularly because they require use of common VRAM input
signals for control  A straight-forward VRAM controller would then
have three separate state machines for each of these 3 modes of
operation.  An arbiter would then be incorporated to act like a
traffic cop allowing only one state machine access to the VRAM
controls.  Fig. 2 shows the state-machine diagram.

      It is assumed that once a display is turned on, it constantly
provides an image and therefore the SDR register continually clocks
data to it.  This is normally the case with most of today's displays.

      Since refreshing the DRAM (mode 2) and Loading the SDR (mode 3)
occur periodically, the idea presented here incorporates these two
actions together.  The result is a simpler and less complex design.
Hence, when it is time to Load the SDR register, a certain amount of
DRAM rows are refreshed (FIG. 3).

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