Browse Prior Art Database

Control Error Checker

IP.com Disclosure Number: IPCOM000111090D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Handlogten, GH: AUTHOR

Abstract

This invention provides a method for checking much of the control logic in a processor (e.g., pipeline control logic, instruction queues, fetch queues, store queues, register renaming logic, register arrays). The checking is closely related to Register Renaming.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Control Error Checker

      This invention provides a method for checking much of the
control logic in a processor (e.g., pipeline control logic,
instruction queues, fetch queues, store queues, register renaming
logic, register arrays).  The checking is closely related to Register
Renaming.

      This invention provides effective error detection on much of
the control logic by pairing a Physical (register renaming) address
with the last Architected address it was associated with.  The
pairing is accomplished in the queues and pipelines by keeping the
Architected addresses (directly from the original instruction) as
well as the Physical addresses (from the rename logic).  The
association is accomplished in the registers by writing associated
Architected addresses (as data) into the physical locations.  The
Architected address becomes a key used to lock and unlock data
throughout the processor.  A fetch or load to a register will write
the fetch's architected address to the array.  For arithmetic, the
Architected and Physical result addresses are sent down the pipelines
as pairs.  When an arithmetic result is written to a register the
Architected address is also written.  Now, the array holds
information indicating what each array element was last used as.
When a store or arithmetic operation enters, the source registers are
renamed to Physical registers.  Later, when the register is read from
the array, the Architected address is checked against the Archite...