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Manufacturing Self-Test of On-Chip Memory Using On-Chip Microprocessor

IP.com Disclosure Number: IPCOM000111105D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 112K

Publishing Venue

IBM

Related People

Dwin, DR: AUTHOR [+4]

Abstract

Manufacturing tests of single-chip microprocessor systems with large amounts of on-chip Random Access Memory (RAM) are difficult because externally generated memory test patterns written and read directly to RAM arrays (whose inputs and outputs are multiplexed directly to chip input/output pins in test mode) are extremely large. Large test patterns may exceed the buffer capacity of a VLSI chip tester, resulting in tests that require an unacceptably large amount of time to complete due to (A) slower accesses of memory through test mode circuitry and (B) constant reloading of VLSI chip tester memory from disk storage.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Manufacturing Self-Test of On-Chip Memory Using On-Chip Microprocessor

      Manufacturing tests of single-chip microprocessor systems with
large amounts of on-chip Random Access Memory (RAM) are difficult
because externally generated memory test patterns written and read
directly to RAM arrays (whose inputs and outputs are multiplexed
directly to chip input/output pins in test mode) are extremely large.
Large test patterns may exceed the buffer capacity of a VLSI chip
tester, resulting in tests that require an unacceptably large amount
of time to complete due to (A) slower accesses of memory through test
mode circuitry and (B) constant reloading of VLSI chip tester memory
from disk storage.

      This problem is solved by providing a technique to allow the
microprocessor to test its own on-chip RAM at full functional
operating speed.

      This memory self-test technique was developed for a Digital
Signal Processor (DSP) subsystem, which incorporates an IBM-designed
DSP microprocessor core, AT/ISA and Microchannel (r) system bus
interfaces, 4K by 24 bits of instruction store RAM, 4K x 16 bits of
data store RAM, Musical Instruments Device Interface (MIDI), and
interfaces supporting a variety of audio bandwidth analog-to-digital
and digital-to-analog devices on a single integrated circuit, or
"chip."  This chip is currently implemented using Level-Sensitive
Scan Design (LSSD) latches in a CMOS circuit technology.

Following is a description of the Technique:

1.  Chip is put in LSSD test mode via test mode input pin level
    selection.  Machine language program for memory testing
    (hereafter referred to as "test program") is loaded into on-chip
    memory via direct writing using address and data inputs which are
    multiplexed onto physical chip input/output pins in test mode.

2.  The chip is switched to normal functional mode via test mode
    input pin level selection.  Waveform(s) of appropriate frequency
    and duty cycle are applied to the chip oscillator inputs.
    Appropriate signals, as required, are sent to input pins on the
    chip to enable operation of the processor.

3.  The test program executes on the microprocessor, writing and
    reading appropriate patterns to and from on-chip memory to
    execute desired memory test algorithm.

4.  The VLSI chip tester control program allows enough time to elapse
    to ensure that the test program has completed its tests (on
    completion of testing, the test program writes test result data
    to an area of memory and enters an "idle state" infinite loop).

5.  The chip is switched back to test mode.  The VLSI chip tester
    control program reads the test result data from th...