Browse Prior Art Database

Using Multiple Memory Images to Run Random Test Program Generator Test Cases in a Multi-Processing Environment

IP.com Disclosure Number: IPCOM000111115D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Merkel, LJ: AUTHOR [+3]

Abstract

Disclosed is a way to run uni-processor test cases on an MP (multi-processor) model without generating pseudo-fails (fails that are not real).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 60% of the total text.

Using Multiple Memory Images to Run Random Test Program Generator
Test Cases in a Multi-Processing Environment

      Disclosed is a way to run uni-processor test cases on an MP
(multi-processor) model without generating pseudo-fails (fails that
are not real).

      In one simulation methodology, billions of cycles are run
weekly on chip simulation models.  Most of these cycles are test
cases generated by RTPG (Random Test Program Generator).  RTPG
generates test cases for a uni-processor only, so something different
had to be done to generate multi-processor test cases.  A program
(MPMERGE) takes three distinct RTPG test cases and merges them into a
single test case for a three way MP.  This program could detect test
cases that attempted to update the same byte...since the order of the
update could not be determined, these tests would be thrown out.
However, the program could not detect when one processor read a byte
that another processor updated.  There is no easy way for MPMERGE to
detect this in an RTPG test case.  This leads to pseudo-fails where
one test case expects the byte to be what it was initialized to, and
the other test case has written it.  RTPG sees these two test cases
as separate, so it detects no problem.  One way to solve this problem
is described below.

      The "memory" that these test cases initialize and load
from/store to is represented in the simulation model by a memory
behavioral.  The memory behavioral designer has comple...