Browse Prior Art Database

Read-Modify-Write Control in Self-Precharged Single Clock DRAM

IP.com Disclosure Number: IPCOM000111123D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 6 page(s) / 143K

Publishing Venue

IBM

Related People

Miyatake, H: AUTHOR

Abstract

The read-modify-write control method proposed here is for a new type of single clock DRAM which is characterized by its self-precharge operation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Read-Modify-Write Control in Self-Precharged Single Clock DRAM

      The read-modify-write control method proposed here is for a new
type of single clock DRAM which is characterized by its
self-precharge operation.

      Aimed at making it realistic to use DRAMs at its minimum cycle
time and at simpler control by users, a self-precharged single clock
DRAM was proposed in prior article.  This newly proposed DRAM is
easier to use than the conventional DRAM because its control is
simpler and it has more affinity with digital logic system, but as it
is cannot support a read-modify-write operation since the precharge
operation automatically starts when its internal state is ready for
the precharge operation.  In the self-precharged single clock DRAM,
an internal main clock named CLK becomes active when the external
clock and/or signals indicates that the DRAM is selected and to be
activated, and it returns to the inactive state when the DRAM can
start its precharge operation.

      In order to realize the read-modify-write operation in the
self-precharged single clock DRAM, the start of the precharge phase
must be delayed until the write operation ends after the read
operation, and the write operation itself after the read operation
must be enabled.

      To do this, an internal signal RMW is provided, and it is
activated at CLKs leading edge when an external signal, /WE(- Write
Enable), is high (indicates the read operation) and another external
signal, /RMW (- Read-Modify-Write), is low (indicates the
read-modify-write cycle).  Otherwise, the internal signal RMW stays
low and DRAM operates as usual.  In the read-modify-write cycle, /WE
need not be high at the CLKs leading edge, but it is natural and
consistent to define as above.

      When RMW is active, i.e., high, the cycle is the
read-modify-write cycle, and the CLKs trailing edge, i.e.,
high-to-low transition, which initiates the precharge phase, is
inhibited.  And DRAM is made to be ready to accept /WEs high-to-low
transition which instructs the DRAM to latch the data to be written
into the DRAM.  Of course, the data receiver circuit of the DRAM is
open to the external data bus.

      If the user need to write data into the DRAM during the
read-modify- write cycle after he read out the previously stored
data, he activates /WE by changing it from the high state to the low
state after he sends the new data to the data bus connected to the
DRAM.  Receiving /WEs high-to-low transition, the DRAM ends the read
operation and starts the write operation, that is, it disconnects the
internal data lines from the off-chip data driver, connect...