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Browse Prior Art Database

Method of Creating Testcases for a Multi-Processor Environment

IP.com Disclosure Number: IPCOM000111130D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Merkel, LJ: AUTHOR [+2]

Abstract

Disclosed is a program that will convert RTPG (Random Test Program Generator) test cases into multi-processor test cases.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method of Creating Testcases for a Multi-Processor Environment

      Disclosed is a program that will convert RTPG (Random Test
Program Generator) test cases into multi-processor test cases.

      In one simulation methodology, RTPG is used to generate
billions of cycles of random simulation to help verify chip designs.
When the MP (multi-processor) simulation problem arose,  these test
cases were to be created.  RTPG can generate uni-processor test
cases, so one way to generate MP test cases is to combine several
RTPG generat-ed test cases into one MP test case.  The MPMERGE
program does this.

      MPMERGE creates a test case with several "domains":  one for
each processor in the target system and one for system memory.  Each
domain may contain initialization or checking for any architectural
element that exists in that domain.  For the processor, this includes
data and instructions for the cache and registers, among others.  The
memory domain contains only memory references.

      MPMERGE has tremendous flexibility in creation of test cases.
First, the test cases used as sources can be one test case repeated
for all processors (giving the maximum amount of coherency conflict),
or separate test cases may be used for each processor.  The test
cases may all be chosen from one file, or may exist in several files.
Also, the way that MPMERGE associates instruction and data references
with the various processors can be varied.  The options are:  one to
one association of a test case's references with the processor that
will be running...