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Optimized Runtime Scrubbing and Sparing Control

IP.com Disclosure Number: IPCOM000111131D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 98K

Publishing Venue

IBM

Related People

Blackmon, LL: AUTHOR [+4]

Abstract

A method for main storage scrubbing and sparing which execute dynamically during system runtime is disclosed. The operations are performed by control logic located on the memory card and their execution appears transparent to the rest of the system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Optimized Runtime Scrubbing and Sparing Control

      A method for main storage scrubbing and sparing which execute
dynamically during system runtime is disclosed.  The operations are
performed by control logic located on the memory card and their
execution appears transparent to the rest of the system.

This invention consists of four key parts:

1.  Make scrubbing and sparing operations look identical.

2.  Treat them both like a normal store command.

3.  Only process them if there are no incoming commands from another
    unit.

4.  Permit variability in the frequency of the operations.

      In this implementation, scrubbing and sparing are closely
interrelated.  Scrubbing consists of a fetch to a DRAM, error
correction if appropriate, and a store back to the DRAM.  It is used
primarily to fix intermittent or soft errors.  It is also used to
predict uncorrectable memory failures before they happen.  During
scrubbing, statistics are gathered on DRAM errors.  If an error
threshold is exceeded during scrubbing, sparing is invoked.  The
general concept involved with sparing is that the memory card
contains an extra DRAM bit per ECC word.  This extra bit is used as a
'spare'.  The statistical information from scrubbing indicates which
bit position should be replaced with the spare bit.  In this
implementation, the spare bit can be steered into any of the other
bit positions for the ECC word (i.e., 'mux' method).  A sparing
'clean-up' operation consists of a fetch to a DRAM, error correction
if appropriate, and a store back to the DRAM using the spare bit in
the appropriate bit position.

      Both of these operations consist of a fetch followed by a
store.  For sparing, a control register is needed to indicate to use
the spare bit and what bit position it replaces.  Both of the
operations start at the beginning of a memory block and increment
sequentially through the block.  Because the operations are similar,
one control model can be used for both of them.  Simply, if the
sparing control register is loaded the operation is a 'clean-up',
otherwise it is a scrub.

      Two key factors permit the simplification and combination of
scrubbing and sparing:  the 'mux' method of sparing and double bit
correct ECC.  In the 'mux' method of sparing, the spare bit can be
steered into any of the other bit positions.  This compares to
another method in which the ECC word is split at the failing bit and
shifted.  If the sparing control register is loaded, the fetch and
the store both use the spare bit.  The data in the spare bit may or
may not cause an ECC error.  Also, another data bit...