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Psuedo-Asynchronous Logic Interface with Optimized Performance

IP.com Disclosure Number: IPCOM000111143D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 107K

Publishing Venue

IBM

Related People

Blackmon, HL: AUTHOR [+2]

Abstract

A psuedo-asynchronous logic interface with optimized performance is disclosed. The basic application characteristic is that the logic on one side of the interface operates at a clock cycle which is a multiple of the clock cycle on the other side of the interface.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Psuedo-Asynchronous Logic Interface with Optimized Performance

      A psuedo-asynchronous logic interface with optimized
performance is disclosed.  The basic application characteristic is
that the logic on one side of the interface operates at a clock cycle
which is a multiple of the clock cycle on the other side of the
interface.

      How to design a logic chip that has an interface which can
operate at a variable pace is described.  A variable pace means that
sometimes the interface clock cycle period is the same as the
internal clock cycle period, and at other times the interface clock
cycle period is a multiple of the internal clock cycle period.

      For example, assume that a rule of a chip interface is that new
data will be received every interface cycle.  When running in
'Normal' mode, from the internal logic's point of view, data is also
being received every internal cycle.  However, in 'Single Step' mode,
from the internal logic's point of view, data may be received every
100 internal cycles.

      A basic assumption of this invention is that the pulse widths
and alignments of the interface clocks and internal clocks are the
same.  The difference is that the interface pace is created by
blocking several of the internal clock cycles.  For example, if the
internal clocks have a 10 nano-second (ns) period with a 5 ns pulse
width, the interface clocks would also have a 5 ns pulse width but
may have a 300 ns period.  When an interface clock pulse occurs, it
overlaps the internal clock pulse exactly.  The interface clock
period can be any multiple of the internal clock period (i.e., 300
ns, 1000 ns, up to infinity (stopped)).

The following describes the basic scenarios and how this invention
handles them.

o   'Slow' partition to 'Fast' partition communication.
     -   The 'Fast' partition must look for (and take action from)
the
        first internal cycle that the value of the signal from the
        'Slow' partition changes.  The 'Fast' partition can delay a
        control input by latching that signal each internal cycle.
        The 'Fast' partition can detect the first cycle the signal
        changes when the input signal miscompares with the delayed,
        latched version of that signal.
     -   No acknowledge signals are needed.  The 'Slow' partition can
        always assume that the 'Fast' partition will 'see' the signal
        change and take action during the first internal cycle.
     -   When handled this way, there is no performance penalty for
        starting an event.  The timing diagrams for the 'Normal' mode
        are still optimized....