Browse Prior Art Database

Clock Control Circuit for Saving a Power

IP.com Disclosure Number: IPCOM000111153D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Ishibashi, K: AUTHOR [+3]

Abstract

Disclosed is a circuit for saving a power dissipation of LSI. Clocks required for the register access are controlled by the address from a controller (e.g., micro processor, host ...). That is, the clock for a register becomes active only when the controller accesses to one.

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This is the abbreviated version, containing approximately 100% of the total text.

Clock Control Circuit for Saving a Power

      Disclosed is a circuit for saving a power dissipation of LSI.
Clocks required for the register access are controlled by the address
from a controller (e.g., micro processor, host ...).  That is, the
clock for a register becomes active only when the controller accesses
to one.

      The Figure shows the concrete circuit for clock control.  The
address of the Controller(1) is decoded by Decoder(2).  This output
signal is used as clock control signal.  When this signal is active,
the clock of Register(3) becomes active.

      The power dissipation of LSI which is designed with synchronous
logic depends on the clock frequency and clock-active time.  The
clock frequency is decided according to LSI specification.  Therefore
this disclosure controls clock-active time.  A very simple circuit
can realize it.