Browse Prior Art Database

Method and Apparatus for Testing Liquid Crystal Display Cell Array

IP.com Disclosure Number: IPCOM000111158D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 88K

Publishing Venue

IBM

Related People

Fujiwara, T: AUTHOR

Abstract

Disclosed is a method and apparatus for testing Liquid Crystal Display (LCD) cell arrays. This method will enable test to see if correct cell capacitors are fabricated on LCD panels, if they are connected to good Thin Film Transistors (TFT), and if the leakage current from the capacitor is small enough, by specifying on/off timing of applied switches and using an integrator.

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Method and Apparatus for Testing Liquid Crystal Display Cell Array

      Disclosed is a method and apparatus for testing Liquid Crystal
Display (LCD) cell arrays.  This method will enable test to see if
correct cell capacitors are fabricated on LCD panels, if they are
connected to good Thin Film Transistors (TFT), and if the leakage
current from the capacitor is small enough, by specifying on/off
timing of applied switches and using an integrator.

      Existing method before this article has tested the cell
capacitor by once charging the cell and then moving, after certain
period, the charge to an integrator referencing ground potential.
This method is effective for volume production of LCD panels,
however, it does not have the capability to isolate defect reasons
into categories such as no cell capacitor fabricated, poor
conductance of TFT, or large leakage current.

This article provides the capability of array cell test and the
capability of cause isolation.

      Fig. 1 shows a part of general structure of LCD cell array
having TFTs.  The PC is a cell plate, which construct a Cell
Capacitor (CC) with CS.  CS is an additional storage capacitor in
case PC will not have enough capacitance.  TR is a TFT.  The gate of
the TFT is connected to a gate line, the drain is connected to a data
line, and the source is connected to the PC.

      Fig. 2 shows the circuit of test apparatus connected to the LCD
cell.  TR is the TFT before mentioned, and the CC is the cell
capacitor.  S2 connects the data line to either ground or the input
of the integrator.  The S2 can be two individual switches.  S1 resets
the integrator.  VDD and VSS are power supply voltages for the
integrator.  VD is the reference voltage, and it is set to LCD cell
potential for actual use or slightly higher, as this potential is
applied to the cell under test.  RP is a protective resistor in case
the output is accidentally connected to a low impedance line, however
it may not be required depending on the operational amplifier
c...