Browse Prior Art Database

Virtual Queue for a Sequential Data Port

IP.com Disclosure Number: IPCOM000111162D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Karim, FO: AUTHOR [+2]

Abstract

An alternate means of sending and receiving data on a superscalar microprocessor other than the memory interface is through a sequential data port. By using a handshaking protocol, data is transmitted or received through the data port one word at a time in a sequential fashion.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Virtual Queue for a Sequential Data Port

      An alternate means of sending and receiving data on a
superscalar microprocessor other than the memory interface is through
a sequential data port.  By using a handshaking protocol, data is
transmitted or received through the data port one word at a time in a
sequential fashion.

      The traditional means of improving performance on these
sequential data ports is to add First-In First-Out (FIFO), physical
queues (Fig. 1).  The FIFO queues allow data to be transmitted or
received in blocks instead of one word at a time.  Adding a physical
queue can be very costly in terms of chip area especially if the chip
has multiple sequential data ports.  Disclosed is a method to use the
existing general purpose register file as a virtual queue for the
sequential data port.

      The typical superscalar microprocessor executes instructions
using data from general purpose registers instead of memory to
improve performance.  These general purpose registers are usually
implemented by using a register file.  Another feature commonly used
is register renaming.  Register renaming allows the execution units
to read and write multiple data words to the same general purpose
register without creating data contention problems.

      Also, in superscalar microprocessors high speed processing can
be achieved from multiple execution units, however, certain
efficiency problems arise.  One such problem may arise by
implementing the traditional FIFO physical queues.  Due to the high
speed processing, the FIFO queues may not be kept full which causes
wasted chip area.  By using the virtual queue technique, renaming,
and extending the size of the register file, the input sequent...