Browse Prior Art Database

Image Processing Circuit

IP.com Disclosure Number: IPCOM000111172D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Nakano, H: AUTHOR [+2]

Abstract

Disclosed is an image compression circuit which generates bi-level run length code with attribute information (e.g., gray scale range of elements of the run) from gray scale image.

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Image Processing Circuit

      Disclosed is an image compression circuit which generates
bi-level run length code with attribute information (e.g.,  gray
scale range of elements of the run) from gray scale image.

This circuit consists of the following two sub-circuits.

1.  A circuit which tags pixels to be compressed.

2.  Another circuit which generates run length code with attribute
    information.  Only tagged pixels must be compressed.

Followings are elements of each run length code generated by the
circuit disclosed.

o   Raster number of the run

o   Horizontal coordinates of the final pixel of the run

o   Length of the run

o   Additional field which indicates gray scale information of the
    run

+--------+ +-----------+ +---------+ +---------+ +----------------+
  | CCD    +-+ A/D       +-+ DIGITAL +-+ LOOK UP +-+ RUN LENGTH
+--+
  | CAMERA | | CONVERTER | | FILTER  | | TABLE   | | CODE GENERATOR |
|
  +--------+ +-----------+ +---------+ +---------+ +----------------+
|
|
+-------------------------------------------------------------------+
  |
  |    +--------------+ +------+ +--------+
  +----+  RUN LENGTH  +-+ MPU  +-+ Main   |
       |  CODE MEMORY | |      | | Memory |
       +--------------+ +------+ +--------+

     Figure.  Block diagram of the video rate labeling system

The Figure shows an example of video rate labeling system.

1.  An image via CCD camera is digitized to gray scale digita...