Browse Prior Art Database

Programmable Cycle Time for a Microcomputer Bus System

IP.com Disclosure Number: IPCOM000111184D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 96K

Publishing Venue

IBM

Related People

Garcia, SE: AUTHOR [+3]

Abstract

A method is described in which several different devices can be efficiently attached to a microcomputer bus, where each of the devices has its own unique access and recovery time constraints. This method uses access and recovery cycle times that are programmable in a bus controller, so that appropriate and efficient cycle timings are generated without requiring external 'Ready' signal generation by each device on the bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Programmable Cycle Time for a Microcomputer Bus System

      A method is described in which several different devices can be
efficiently attached to a microcomputer bus, where each of the
devices has its own unique access and recovery time constraints.
This method uses access and recovery cycle times that are
programmable in a bus controller, so that appropriate and efficient
cycle timings are generated without requiring external 'Ready' signal
generation by each device on the bus.

      When several devices are connected together through a
microcomputer bus, the bus controller must generate bus cycles,
whether they be, e.g., read cycles, write cycles or Direct Memory
Access (DMA) cycles, in such a manner as to give the device that it
is accessing enough time to respond correctly.

In order to respond correctly each device must be allowed:

o   access time, measured from the start of the cycle, which allows
    the device to provide correct data, in the case of a read, or
    properly latch the data given to it, in the case of a write, and

o   recovery time, measured from the end of the cycle, which allows
    circuitry in the device to settle before the device is capable of
    handling another bus access.

      If these devices do not respond in the same amount of time, the
bus controller typically handles this in one of two ways:

1.  All devices are accessed by bus cycles designed for the slowest
    device that is connected to the bus.

2.  A 'Ready'/'Not Ready' indication is required from the devices to
    the bus controller.

      The first of these methods can be extremely inefficient, since,
for all practical purposes, all devices are forced to run as slow as
the slowest device that can be put on the bus.  If there is a
significant difference in the actual response times of the slowest
and fastest devices, the performance of the bus can suffer
drastically.

      The second method listed above requires extra circuitry with
each device, or one circuit for multiple devices with some type of
look-up table, must inform the bus controller that the device is 'Not
Ready' as soon as it is accessed.  The circuit must then hold the bus
controller in that state until enough time has passed for the device
to respond correctly, at which point it may then allow the bus
controller to proceed by informing it that the device is 'Ready'.  It
should be noted that this circuitry must not only account for the
access time as stated above, but but it must also allow for the
recovery time...