Browse Prior Art Database

Full Swing Performant Data Compression for Abist

IP.com Disclosure Number: IPCOM000111188D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 95K

Publishing Venue

IBM

Related People

Rougeon, C: AUTHOR

Abstract

Fig. 1 shows the global synoptic of a new concept of data compression circuit used in a 128X80 SRAM (described here as an example). It consists of the assembly of sixteen 10 inputs pseudo NOR circuits and a 16 inputs pseudo NAND circuit. The number of logic layers is 2, decreasing the propagation delay as compared with a standard circuit.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Full Swing Performant Data Compression for Abist

      Fig. 1 shows the global synoptic of a new concept of data
compression circuit used in a 128X80 SRAM (described here as an
example).  It consists of the assembly of sixteen 10 inputs pseudo
NOR circuits and a 16 inputs pseudo NAND circuit.  The number of
logic layers is 2, decreasing the propagation delay as compared with
a standard circuit.

      The first logic layer reduced the amount of comparisons between
array data bits and the expected data.  As all even and odd data out
bits must respectively be equal at every cycle (even bits at 0 and
odd bits at 1 for instance), it is possible to compare at the same
time all even bits to the single even expected data (0) and all odd
bits to the single odd expected data (1).  Here, to perform this
global comparison, NOR logic function are used.  This only allows to
check that no logic one appears in the data flow when 0 are expected.
Thus to detect a fail when a logic 1 is expected, the global
comparison is applied on complement data out bits (Table).

      In theory, 4 NOR logic circuits would be enough, one for each
expected data (true and complement).  But to meet performance and
test requirement, the number of inputs for each NOR is limited to 10.
For a word depth of 80 bits, that results in 16 NOR circuits.

      If there is no fail, all the NOR outputs are high, and the NAND
output is low.  If a fail occurred, the concerned NOR output is set
to 0, turning the RESULT pin high.

      According to the expected data, there is always half of all NOR
circuits that are inactive.  Nevertheless, their outputs must be high
as if there is no fail.  All the 16 NORs outputs (true and
complement) are connecte...