Browse Prior Art Database

Common Pins for Hardware Setup Input and Functional Mode Output

IP.com Disclosure Number: IPCOM000111207D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Chan, FL: AUTHOR [+4]

Abstract

Disclosed is the use of bi-directional drivers associated with I/O pins, to transmit input signals during Power-On Reset (POR) enabling various functional modes during power up procedures, and to transmit functional output signals during normal operation after POR. In this way, in situations where hardware setup can be performed in the system during power-on reset, a need for additional pins for setup procedures is eliminated, often eliminating a need to increase the package size of a VLSI chip. With this method, bi-directional drivers are used as devices having three states during POR, with the input portion of the pin being used to setup a chip function.

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Common Pins for Hardware Setup Input and Functional Mode Output

      Disclosed is the use of bi-directional drivers associated with
I/O pins, to transmit input signals during Power-On Reset (POR)
enabling various functional modes during power up procedures, and to
transmit functional output signals during normal operation after POR.
In this way, in situations where hardware setup can be performed in
the system during power-on reset, a need for additional pins for
setup procedures is eliminated, often eliminating a need to increase
the package size of a VLSI chip.  With this method, bi-directional
drivers are used as devices having three states during POR, with the
input portion of the pin being used to setup a chip function.

      Hardware setup is accomplished during POR, pulling up or down
bi-directional setup pins.  A further combination of two
bi-directional drivers allows a system to setup multiple functions
within a chip during POR.  During normal operation following setup,
the output drivers associated with these pins are enabled, so that
the pins can be used as normal functional outputs of the chip, while
input paths through these pins are unused.

      For example, this mechanism is used to activate the error
detection logic in a bus interface chip in a system supporting an
upgrade processor, while providing an additional function of
switching to the planer processor if the upgrade processor is not
operating correctly.  This function is enabled i...