Browse Prior Art Database

Off-Chip Receiver Insensitive To CMOS Process Variation

IP.com Disclosure Number: IPCOM000111260D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 69K

Publishing Venue

IBM

Related People

Hoffman, JA: AUTHOR

Abstract

Disclosed is a circuit design technique for minimizing normal process variations effects on CMOS logic circuits, notably TTL Off Chip Receivers used in VLSI.

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Off-Chip Receiver Insensitive To CMOS Process Variation

      Disclosed is a circuit design technique for minimizing normal
process variations effects on CMOS logic circuits, notably TTL Off
Chip Receivers used in VLSI.

      During the design of Off-Chip Receives (OCR),normal CMOS
process variation due to the independent variations of PMOS and NMOS
transistors result in wide variation in the OCR input threshold
levels.  Current design practice is in Fig. 1.  An OCR typically
consists of an inverter chain to provide level shifting from external
TTL voltage levels to CMOS levels required internally by the VLSI.
Noise immunity in provided by the use of a feedback transistor from
the output of the second stage to the output of the first stage.

      The individual device sizes of the first stage and the feedback
transistor determine the input threshold voltage of the OCR.

      This invention drastically reduces the sensitivity of the
circuit to the independent variations of the NMOS and PMOS devices
while maintaining the desirable features of the CMOS technology such
as low power dissipation.  One embodiment of this design approach is
shown in Fig. 2.

      The process variations normally expected in CMOS technology
result in variations of the drain to source resistances of the NMOS
and PMOS devices.  These variations are the principal causes of the
threshold variations in the circuit.  The addition of an NMOS
transistor to the pull-up path total...