Browse Prior Art Database

Copy Mode Control Method for Semiconductor Random Access Memory Device

IP.com Disclosure Number: IPCOM000111263D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 5 page(s) / 202K

Publishing Venue

IBM

Related People

Miyatake, H: AUTHOR

Abstract

Disclosed is a copy mode control method for semiconductor RAMs in which memory cells are arranged in a two-dimensional array which has sense/latch circuits along one dimension to amplify and retain the read-out data. Data read out and latched at the sense amps are not reset but retained, and copied to other row addresses selected in the successive cycles in the copy mode.

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This is the abbreviated version, containing approximately 29% of the total text.

Copy Mode Control Method for Semiconductor Random Access Memory Device

      Disclosed is a copy mode control method for semiconductor RAMs
in which memory cells are arranged in a two-dimensional array which
has sense/latch circuits along one dimension to amplify and retain
the read-out data.  Data read out and latched at the sense amps are
not reset but retained, and copied to other row addresses selected in
the successive cycles in the copy mode.

      First, the new operation mode named copy mode is explained.  In
semiconductor RAMs which has the memory cell array organization
mentioned above, the data stored in all cells along the selected word
line, which is selected by a row address, are read out on the bit
line pairs, and amplified and latched by the sense amps.  Then, a bit
line pair is selected by a column address and the selected read-out
data transferred from the bit line pair to the data line pair (read
operation) or the data to be written are transferred from the data
line pair to the selected bit line pair (write operation).  Note that
here if there are n bit line pairs in the array, n bits of data are
latched at the sense amps.

      In conventional RAMs, after the data exchange above the word
line is reset and then sense amps are also reset to their stand-by
states.  This ordinary RAM internal operation is shown in the timing
chart of RAM's major signals in Fig. 1.  In this Figure, -CE is the
primary clock to the RAM, which will be -RAS in case of the
conventional DRAM, and CLK is the internal main clock in the RAM.

      The copy mode here utilizes the latch function of the sense
amps, and RAM users can copy data from a row address to other row
addresses.  In this copy mode, the data read out and latched at the
sense amps in the first cycle are not reset but retained on bit line
pairs as well as at the sense amps until the end of the copy mode,
and in the successive cycles in the copy mode selected are different
row addresses to which the data at the first row address are to be
copied.  Thus data are copied from the first selected row address to
other row addresses selected in the successive cycles in the copy
mode.  Note that if there are n bit line pairs activated in the
array, n bits of data are copied at the same time.  This is very
useful in the application where all memory locations are filled with
the same data, such as the screen clear operation of the video
processor.

      In any cycle during the copy mode data can be written at the
column address specified by the user from the outside of the RAM, and
those data are then latched at the sense amp at that column address
and copied to other row addresses selected in the successive cycles
in the copy mode.  In this case, too, data at column addresses other
than that at which the write operation was done are not changed but
retained, and copied to other row addresses.

      The control method for this copy mode follows.  This con...