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Improvements In The Sacrificial Substrate Burn-In Methodology for Known Good Die

IP.com Disclosure Number: IPCOM000111269D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Bhattacharya, S: AUTHOR [+3]

Abstract

Sacrificial substrate burn-ins of semiconductor chips are performed to weed out weak chips which would otherwise have infant mortality in customer's machines. The chip burn-in process is particularly needed for Multi-Chip Modules (MCMs) where multiple chips are joined to one substrate and any post chip joining failure would be cause for rework and increased cost.

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Improvements In The Sacrificial Substrate Burn-In Methodology for
Known Good Die

      Sacrificial substrate burn-ins of semiconductor chips are
performed to weed out weak chips which would otherwise have infant
mortality in customer's machines.  The chip burn-in process is
particularly needed for Multi-Chip Modules (MCMs) where multiple
chips are joined to one substrate and any post chip joining failure
would be cause for rework and increased cost.

      In the current sacrificial burn-in process shown in Fig. 1,
flip chip 1 with 5 mil C4 pads is joined to the metallized ceramic 2
by PbSn C4s 3.  The pad on the substrate side 2 is of the order of 2
mils, less than half the diameter of the pad on the chip side 3.  The
ensemble is burned-in where the chip is electrically powered at an
elevated temperature for several days.  Following the burn-in, the
chip 1 is mechanically sheared off the metallized ceramic substrate
2.  The 2 mil diameter pad on the substrate side ensures failure at
the substrate interface and thus preserves the full C4.  However,
because of the small C4 pad on the substrate side, a slight
misalignment of the chip relative to the substrate results in a high
resistance joint or a complete open.  Frequently, the C4s short to
the adjacent metal lines as well.  This lack of self alignment
capability because of small substrate pad causes particularly low
yield in logic chips with high I/O count.  An additional problem is
the mechanical removal...