Browse Prior Art Database

Digital Power MOSFET Circuit

IP.com Disclosure Number: IPCOM000111272D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 6 page(s) / 207K

Publishing Venue

IBM

Related People

Mussenden, GA: AUTHOR

Abstract

Described is a hardware circuit implementation to provide a fully digital amplifier configuration utilizing power metal oxide silicon field effect transistors (MOSFETs). The design reduces power consumption requirements by utilizing current linear power amplifier techniques that rely on biasing the output transistors in a partially conduction state so as to overcome the effects of crossover distortion.

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Digital Power MOSFET Circuit

      Described is a hardware circuit implementation to provide a
fully digital amplifier configuration utilizing power metal oxide
silicon field effect transistors (MOSFETs).  The design reduces power
consumption requirements by utilizing current linear power amplifier
techniques that rely on biasing the output transistors in a partially
conduction state so as to overcome the effects of crossover
distortion.

      Typically, the MOSFET devices have been utilized in cellular
architecture so as to provide current sensing of the overall current
flowing through a device.  This is generally performed by means of
mirror-sensing of the current flowing through a few of the MOSFET
cells.

      Consider a MOSFET device composed of 2 sup N-1 Individual Cell
Transistors (ICTs), where N is an integer and N ge 1.  When the 2 sup
N-1 ICTs are allotted into N groups, the first group contains one
cell and the second two, kth group, contains 2 sup <k-1>, and the
last group contains 2 sup <N-1> cells.  Within each group, the gates
of each of the ICTs that compose the group are connected together to
a terminal on the aggregate MOSFET device.

      The aggregate MOSFET device will consequently have N terminals
controlling the collective gate of the N groups.  Also, the MOSFET
device will have collective drain and source terminals which, as in
typical power MOSFETs, are connected to the drains and sources of all
of the ICTs comprising the aggregate device.  The result is a device
with N+2 terminals.  If the gate source voltage of a particular ICT
is V sub <G S>, the saturation current for that cell is I sub <i c t
s a t>.  A group of ICTs composed of 2 sup <(k-1)> cells will have a
saturation current of 2 sup <(k-1)> x I sub <i c t s a t>.  This will
result in an N group MOSFET device that will be a digital-to-analog
converting transistor, where the aggregate saturation (AGSAT) current
is

              I sub <a g s a t> = I sub <i c t s a t> x  sum from i=1
to N of <Alpha sub i> x 2 sup <k-1>

The A sub i is a 0 or 1, depending on whether the ith bit of the
N-bit-wide word to be converted is a 0 or 1.

      If one more ICT is added to the aggregate transistor, it would
be composed of 2 sup N ICTs.  The drain terminals of this additional
ICT is connected to the drain terminal of the aggregate device
together with the drain terminals of all the other ICTs.  The gate
and source terminals of the additional ICT are brought out using
separate terminals on the aggregate device.

      Fig. 1 shows how the die for an N=6 transistor would look with
64 cells.  The sensing ICTs and the smaller groups are close to the
center of the die.  The larger group is toward the periphery of the
die.  The layout is designed in this fashion for two reasons:  first,
having the sensing ICT close to the center improves its tracking in
relation to all the other ICTs; second, the ICTs composed of the
smalle...