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Browse Prior Art Database

Using Dual and Mappable Spare Bus

IP.com Disclosure Number: IPCOM000111281D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 6 page(s) / 250K

Publishing Venue

IBM

Related People

Pita, FJ: AUTHOR [+2]

Abstract

In order to provide fault tolerance on a system utilizing a bus architecture, the data and address buses require alternative paths. This backup path should include each entity in the system, including all cards and the backplane or interconnection mechanism used. Fully redundant hardware solutions are too expensive, complex, and by design can only guarantee tolerance of a single fault. Bus sparing schemes are less costly, but still rather complex in attaining only single fault survival.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 24% of the total text.

Using Dual and Mappable Spare Bus

      In order to provide fault tolerance on a system utilizing a bus
architecture, the data and address buses require alternative paths.
This backup path should include each entity in the system, including
all cards and the backplane or interconnection mechanism used.  Fully
redundant hardware solutions are too expensive, complex, and by
design can only guarantee tolerance of a single fault.  Bus sparing
schemes are less costly, but still rather complex in attaining only
single fault survival.

      Described is a dual sparing method that provides notable
advantages over presently existing implementations.  One example of
such a bus is Micro Channel*, which has address and data buses made
up of 9-bit bus segments, 8 signals plus 1 parity bit.  Dual spare
bus segments are added as flexibly mapped modules, as shown in Fig.
2.  Each spare bus segment can independently replace any faulty bus
segment.  Faults need only be isolated down to the errant bus segment
(not to an individual bit).  Tolerance is achieved against two
independent or sequential hardware faults.  This method provides
benefits by providing improved fault tolerance, efficient
implementation, and minimized design complexity.  Net improvement in
overall system availability is maximized.  Though this invention was
developed for the XCS Micro Channel bus, its benefits are applicable
to a broad scope of bus topologies.

      As shown in Fig. 1, the Micro Channel Bus architecture details
36 data signals, 36 address signals, and several control signals.
This invention can be applied to any such bus that can be subdivided
into equivalent segments (such as bytes, words, or groups).  An
application of the method to Micro Channel is shown in Figs. 1 and 2.
In this example, a bus segment is represented with 9 bits (8 signals
plus parity).  As noted, the address and data buses each consist of
four bus segments.  Duplicating the address and data buses would
result in the addition of 72 complete signal nets.  This would
require extra backplane wiring, card and backplane connectors,
terminators, and corresponding drivers and receivers.  While this
provides full redundancy against single points of failure, it adds
significant cost and complexity to the design of the attachment
cards, backplane and connectors.  In most cases, the design must be
radically altered to incorporate large duplex buses and their
associated controls.

      There are several alternative ways to provide redundancy on a
system bus and backplane.  They include architecting a backplane
protocol for fault tolerance, fully redundant bus designs, and signal
sparing [1,2,3].  Among the disadvantages of a fault-tolerant
protocol are complexity, high product and development costs, and a
resultant proprietary system with limited hardware interoperability.
The advantages of signal sparing over full redundancy are obvious.
Bus sparing reduces connector pincount, t...