Browse Prior Art Database

Hybrid Reducdancy Direct-Access Storage Device Array with Design Options

IP.com Disclosure Number: IPCOM000111308D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 8 page(s) / 298K

Publishing Venue

IBM

Related People

Styczinski, DA: AUTHOR

Abstract

Disclosed here is a Direct-Access Storage Device (DASD) array which is less expensive than a strictly mirrored array and which performs better than a strictly check-summed (parity) array. A design option uses part of the mirrored portion of the array (when it is larger than the data portion of a DASD) to supply a spare DASD which can be used to restore redundancy when a single DASD fails.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 21% of the total text.

Hybrid Reducdancy Direct-Access Storage Device Array with Design
Options

      Disclosed here is a Direct-Access Storage Device (DASD) array
which is less expensive than a strictly mirrored array and which
performs better than a strictly check-summed (parity) array.  A
design option uses part of the mirrored portion of the array (when it
is larger than the data portion of a DASD) to supply a spare DASD
which can be used to restore redundancy when a single DASD fails.

      The invention consists of an array of n DASD, an intelligent
controller including suitable buffers, and a Non-Volatile RAM
(NVRAM).  The array is divided into a check-sum domain and a mirror
domain each spread uniformly across the n DASD.  The user addressable
data (addresses 1 to MAXLRN) is mapped to the check-sum domain to
provide any desired RAID type of check-sum array (3, 5, or another).
The NVRAM provides an address map of addresses diverted from the
check-sum domain to the mirror domain.  The NVRAM is required to be
large enough to map all of the addresses of the mirrored domain.
Data is written to the mirror domain and an address map stored in the
NVRAM; at a later time the data is staged to the check-sum domain.
Reads are from the mirror domain or the check-sum domain as
necessary.

      Each DASD comprising the array is divided into three areas, the
D-area containing the user data, the C-area containing the check-sum,
and the M-area containing the staged mirrored data destined for the
D-area.

      An interesting (hot spare) design option is available when the
total size of the n M-areas is larger than one DASD so that when one
DASD breaks, a portion of each M-area can be deployed as additional
D-area and C-area so check-sum redundancy is restored until repairs
are made.  There will be some loss of performance because the size of
the M-area is reduced and there are n-1, rather than n, access arms
until the repair is made.

Features of the Invention

o   With hot spare design option

    -   At any time all of each DASD, including the spare portion, is
        providing some service to the array.

    -   When a DASD breaks, data is redeployed so that check-sum is
        restored to the remaining DASD.  This causes the reliability
        to be less dependent on the time to repair which is extremely
        IMPORTANT because the array failure rate is directly
        proportional to time to repair.

o   With or without hot spare design option

    -   Write response time for the hybrid array is like that of a
        mirror array(1)  with storage efficiency near that of a
        check-sum array.

    -   Read response time is between the read response time of
        mirror arrays and check-sum arrays.

    -   Performance smoothing occurs because staging from the mirror
        domain to the check-sum domain is delayed to less busy
        period...