Browse Prior Art Database

Maintaining Chip Failure Correction/Detection after Bit Sparing

IP.com Disclosure Number: IPCOM000111330D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 70K

Publishing Venue

IBM

Related People

Coteus, PW: AUTHOR [+4]

Abstract

In most DRAMs today the address is not allowed to propagate into the chip (receivers are disabled) or the address is not allowed to propagate very far into the chip (the address is blocked) when RAS is inactive. This reduces the power that the chip uses because the number of circuits that see the address change is limited. Other chips have the address path enabled which will use more power. However, allowing the address to propagate into the chip when RAS is inactive will reduce the RAS access time.

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Maintaining Chip Failure Correction/Detection after Bit Sparing

      In most DRAMs today the address is not allowed to propagate
into the chip (receivers are disabled) or the address is not allowed
to propagate very far into the chip (the address is blocked) when RAS
is inactive.  This reduces the power that the chip uses because the
number of circuits that see the address change is limited.  Other
chips have the address path enabled which will use more power.
However, allowing the address to propagate into the chip when RAS is
inactive will reduce the RAS access time.

      This method provides a means to control whether a DRAM is in a
"Fast Access" mode or a "Low Power" mode.  In the Fast Access mode
the address receivers would be powered up and the address would be
allowed to propagate into the chip for a fast RAS access.  In the Low
Power mode RAS falling would enable the address path (possibly
including enabling the address receivers).  This method uses a
programmable bit, wire bond, fuse, or other method to allow the chip
to operate in the Fast Access mode (with the address path enabled at
RAS time or in a Low Power mode where RAS falling activates the
address path.