Browse Prior Art Database

Secondary Cache Daughterboard Assembly for 486/386-Based Personal Computers

IP.com Disclosure Number: IPCOM000111338D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Dunnihoo, JC: AUTHOR

Abstract

Proposed is a design for implementing L2 cache on a daughterboard that derives all necessary control and data signals through a standard microprocessor socket. This design provides a means to add external cache function to non-cached computer systems. It also provides the computer manufacturer with the capability to differentiate low- and high-end models without the need for additional cache-upgrade hardware.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 63% of the total text.

Secondary Cache Daughterboard Assembly for 486/386-Based Personal
Computers

      Proposed is a design for implementing L2 cache on a
daughterboard that derives all necessary control and data signals
through a standard microprocessor socket.  This design provides a
means to add external cache function to non-cached computer systems.
It also provides the computer manufacturer with the capability to
differentiate low- and high-end models without the need for
additional cache-upgrade hardware.

      Currently, external cache must be designed directly and
permanently into a motherboard design.  If cheaper, lower performance
versions of the card are to be offered, then the permanent cache must
be designed with an option to disable it and leave those components
off the board.  However, this eliminates only the cost of the
components from the low-end board.  Engineering costs and cycle time
detractors must still be shared by all levels of the card.

The proposed design has the following advantages over prior art:

1.  No extra components or sockets required on the motherboard.

2.  Design costs for cache subsystem can be divided over just those
    high-end products that use it.

3.  Cache/no-Cache features can be determined at system-build level,
    just like hard drive size, modem/no-modem, etc. (build to order).

4.  Existing and competing designs could be "supercharged" with a
    combination cache and DX2 or IBM Blue-Lightning processor
    upgrade.

5...