Browse Prior Art Database

Improving Read Throughput on a Bursting Bus

IP.com Disclosure Number: IPCOM000111383D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Ackerman, E: AUTHOR [+5]

Abstract

By reducing the "read data" overhead states of a synchronous bursting 32-bit (4 byte) multiplexed address/data bus, the read data throughput of the bus can be increased.

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This is the abbreviated version, containing approximately 53% of the total text.

Improving Read Throughput on a Bursting Bus

      By reducing the "read data" overhead states of a synchronous
bursting 32-bit (4 byte) multiplexed address/data bus, the read data
throughput of the bus can be increased.

      For a general synchronous 32-bit (4 byte) multiplexed
address/data bus that supports bursting, an address phase occurs to
start the data transfer.  Following the address phase there may be
from 0 to n number of additional states that can be described as the
wait phase.  After the wait phase of a bursting operation, several
data words can be transferred.  Following the multiple data words
being transferred, there is often a recovery state or recovery phase
that must also occur.  For this type of bus operation, the initial
address is stored and implicitly incremented for every data word that
is transferred.  This general bursting operation is illustrated in
the graph of Fig. 1.

      When a sub-word (1, 2 or 3 bytes) data transfer must take place
on the initial cycle of a data transfer, the efficiency of this
bursting bus is greatly decreased.  Sub-words require an address
phase, the wait phase and only a single data transfer followed by the
recovery phase.  A sub-word transfer is illustrated in the graph of
Fig. 2.  Therefore, when a block read is attempted and the starting
address is not 4-byte word aligned, a sub-word data transfer must
occur prior to a bursting data transfer.  This sub-word transfer must
take place to align the...