Browse Prior Art Database

Fan-Node Oriented Fault Modeling Technique

IP.com Disclosure Number: IPCOM000111387D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 67K

Publishing Venue

IBM

Related People

Dibrino, M: AUTHOR [+2]

Abstract

Disclosed is a technique that uses the concept of fan-node to improve the efficiency of automatic fault model generation algorithm.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 62% of the total text.

Fan-Node Oriented Fault Modeling Technique

      Disclosed is a technique that uses the concept of fan-node to
improve the efficiency of automatic fault model generation algorithm.

      A circuit schematic that consists of transistors is first
scanned to determine 'fan-nodes'.  A 'fan-node' is a node that has
more than one 'source' or 'parent'.  To illustrate this technique, a
circuit schematic of CSA3T2 is converted to a more readable fashion
shown in Fig. 1.

      For output node SUM, node ANEW and BNEW are called 'fan-nodes'
of the output SUM.  To generate a set of boolean equations that
represents the fault model of a circuit schematic, the following
algorithm is followed.

      (a) Starting from the output node SUM, trace all current paths
to all fan-nodes.  In this example, the output SUM is first traced to
node G through an inverter.  The nodal equations from node G to
fan-nodes ANEW and BNEW are shown as follows:

 ANEW : (S1)(S2) + (S1N)(S2N)  /$G$/

 BNEW : (S1)(S2N) + (S1N)(S2)  /$G$/

      (b) Fan-node ANEW is then trace to 'ground (GND)' by relating
ANEW and GND through the following nodal equation:

 GND : (S3)(RN)   /$ANEW$/

Similarly, BNEW is related to GND by the following nodal equation:

 GND : (S3N)(RN)  /$BNEW$/

      (c) From the above nodal equations, one can derive the 'boolean
representation' of fault model as follows:

    NET98 = (S3N)BNEW + (S3)ANEW

    ANEW = (S1)(S2) + (S1N)(S2N)

    BNEW = (S1)(S...