Browse Prior Art Database

Parity-Predict Mechanism for Single-Bit Register Update

IP.com Disclosure Number: IPCOM000111415D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 22K

Publishing Venue

IBM

Related People

Bergey, AL: AUTHOR

Abstract

This invention is a parity-predict mechanism that allows correct parity to be maintained in a register that is always modified one bit at a time.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Parity-Predict Mechanism for Single-Bit Register Update

      This invention is a parity-predict mechanism that allows
correct parity to be maintained in a register that is always modified
one bit at a time.

See Figure  Parity Predict Mechanism for Single-Bit Register Update

      Before an operation begins, the register is reset to all zeros
in the data bits and good parity in the parity bit.

      Whenever a bit is modified, hardware exclusive-ORs 1, receive
the old value of the data bit 4, the new value of the data bit 3, and
the old value of the parity 2 together, as shown in the Figure.

The result is loaded into the parity bit 2 at the same time that the
new data bit 4 is loaded.

This algorithm maintains good parity in the register as it is
updated.