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Browse Prior Art Database

Cache Memory Data Bus to System Bus Interface

IP.com Disclosure Number: IPCOM000111424D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 130K

Publishing Venue

IBM

Related People

Price, WE: AUTHOR [+3]

Abstract

Disclosed is a method for interfacing a cache memory data bus to a narrower system bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 50% of the total text.

Cache Memory Data Bus to System Bus Interface

      Disclosed is a method for interfacing a cache memory data bus
to a narrower system bus.

      As shown in Fig. 1, a level 2 cache function may be provided in
a conventional manner through the use of a CPU/cache core 10,
including a processor 12, a cache controller 13, and cache SRAM
(static random access memory) modules 14.  For example, an Intel
store-in cache chipset, with a C5 cache controller and C8 cache SRAM
modules can be used in this way.  Using this chipset, the memory data
bus width can be configured to a 32-, 64-, or 128-bit mode.  Thus,
these large memory data bus widths must be interfaced with a narrower
system bus 15, which may be, for example, 8 or 16 bits wide.

      A problem arises when data must be presented on the memory bus
in the full size in which it is requested.  For example, if the
memory data bus to SRAM modules 14 is configured for 32 bits while
system bus 15 is only 8-bits wide, and if CPU/cache core 10 requests
all 32 bits, various tasks associated with running multiple 8-bit
cycles on the system bus to present data in a 32-bit format must be
performed by logic external to CPU/cache core 10.  Specifically, a
bus controller 16 is required for this purpose, along with circuits
18 including data steering buffers and data latches.

      Fig. 2 is a timing diagram showing a data read occurring as
described in the above example.  With the 32-bit memory data bus,
four system bus cycles are required to receive data from an 8-bit
format.  As these four cycles are run, 8-bit data, indicated as A, B,
C, or D, is steered into the correct memory data byte and strobed, by
the SYSTEM DATA READY signal, in latches within circuits 18.  In Fig.
2, a "don't care" condition occurs at the locations where data bytes
are transferred during the times indicated by shading.  At the
completion of the cycle, the data is strobed by the MEOC# (memory end
of cycle) signal, being transferred in to the  SRAM modules in a
32-bit format from the latches in circuits 18.  Thus, the MEOC#
signal acts as a ready signal to the SRAM modules on the 32-bit
transfer.  This signal is also asserted as required to switch the
internal SRAM buffers to the next set of data.  In this example, the
SRAM signal, MBRDY, remained inactive, since only one 32-bit word was
transferred.  In cases where a line fill is taking place MBRDY
strobes the memory data into the SRAM modules for all 32-bit
transfers except the last one, in which MEOC# is used.

      As shown in Figs. 3 and 4, this kind of data transfer can
alternately be performed without a need for external latches,
providing benefits in cost, printed circuit board space, and reduced
memory bus delay.  These advantages are substantially increased in
applications having a memory data bus configured for 64- and 128-bit
bus widths.

      Referring to Fig. 3, in this simplified circuit, cache SRAM
modules 20, a bus controll...