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Browse Prior Art Database

Hot Plugging Bus Device

IP.com Disclosure Number: IPCOM000111471D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 92K

Publishing Venue

IBM

Related People

Morris, N: AUTHOR

Abstract

Disclosed is an electronic circuit that allows a device to be plugged onto a bus without disturbing other devices on the bus. It can be used with various serial or parallel bus types, generates a hot-plug reset request pulse to the host system, uses only 3 differing pin-lengths in the connector and draws no DC power until after the hot-plug reset request pulse.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Hot Plugging Bus Device

      Disclosed is an electronic circuit that allows a device to be
plugged onto a bus without disturbing other devices on the bus.  It
can be used with various serial or parallel bus types, generates a
hot-plug reset request pulse to the host system, uses only 3
differing pin-lengths in the connector and draws no DC power until
after the hot-plug reset request pulse.

      The method is to generate a RESET signal from a card that has
no power on it, i.e., use a FET which is normally ON with no voltage
applied to the gate.  The FET is connected from ground to the RESET
line; thus, this line is always pulled down when there is no power
applied to the card.   Normally when plugging in a card on a live bus
to prevent data corruption loss, the sequence of connections must be
RESET (low), DATA BUSS, RESET (high), also if a KELLS card is used,
ground must be applied before 38V.   One solution could be to use
five different length pins; this device uses only three.

      Computer and instrumentation systems need to be able to support
concurrent maintenance.  Devices should be able to be hot-plugged
without disturbing the operation of the overall system, which is
difficult to achieve when a group of devices share the same computer
data and/or address buses.   Like previous designs, this invention
uses groups of short, medium, and long pins to stagger the
connections in time.   The pins are selected to follow this plug
sequence:

1) Long pins make contact.  A reset request signal is asserted.

2) Medium pins make contact.  Bus and control signals are connected.

3) Short pins make contact.  The reset request signal is released.

The unplug sequence is:

1) Short pins disconnect.  A reset request signal is asserted.

2) Medium pins disconnect.  Bus and control signals disconnect.

3) Long pins disconnect.  The reset request signal is released.

      The system is designed to avoid any unexpected errors on the
shared data/address buses.  When the reset request signal is active,
all buses are quiesced by forcing a suitable reset signal.

      The advantage of this design over previous designs is that all
DC power supplies to the device can be in the short pin group to
ensure that the only activity in the dev...